82443ZX Datasheet, PDF (94/116 Pages) Intel Corporation – Intel® 440ZX AGPset: Host Bridge/Controller

Functional Description
4.2.4
4.3
4.3.1
Frame Buffer Memory Support (USWC)
To allow for high speed write capability for graphics, the Pentium II processor family has
introduced USWC memory type. The USWC (uncacheable, speculative, write-combining)
memory type provides a write-combining buffering mechanism for write operations. A high
percentage of graphics transactions are writes to the memory-mapped graphics region, normally
known as the linear frame buffer. Reads and writes to USWC are non-cached and can have no side
effects.
In the case of graphics, current 32-bit drivers (without modifications) would use Partial Write
protocol to update the frame buffer. The highest performance write transaction on the CPU bus is
the Line Write.
DRAM Interface
The 82443ZX integrates a main memory DRAM controller that supports a 64-bit or 72-bit (64-bit
memory data plus 8 ECC) DRAM array. However, the 82443ZX does not support ECC. The
DRAM types supported are Synchronous (SDRAM) and Extended Data Out (EDO). The 82443ZX
does not support mixing of SDRAM and EDO. When the CPU bus is running at 100 MHz, the
82443ZX DRAM interface runs at 100 MHz (SDRAM only). When the CPU bus is operating at 66
MHz, the 82443ZX DRAM interface runs at 66 MHz (SDRAM or EDO). EDO DRAM technology
is supported in mobile designs only at 66 MHz. The DRAM controller interface is fully
configurable through a set of control registers. Complete descriptions of these registers are given in
the Register Section. A brief overview of the registers which configure the DRAM interface is
provided in this section.
The 82443ZX supports industry standard 64/72-bit wide DIMM modules with SDRAM and EDO
DRAM devices. The fourteen multiplexed address lines, MA[13:0], allow the 82443ZX to support
1M, 2M, 4M, 8M, and 16M x72/64 DIMMs. Both symmetric and asymmetric addressing is
supported. The 82443ZX has eight CS# lines, used in pairs enabling the support of up to four 64/
72-bit rows of DRAM. For write operations of less than a QWord in size, the 82443ZX will
perform a byte-wise write. The 82443ZX targets 60 ns EDO DRAMs and SDRAM with CL2 and
CL3 and supports both single and double-sided DIMMs. When using EDO DRAM, up to 4 rows of
memory are supported. The 82443ZX provides refresh functionality with programmable rate
(normal DRAM rate is 1 refresh/15.6ms). When using SDRAMs the 82443ZX can be configured
via the Paging Policy Register to keep multiple pages open within the memory array. Pages can be
kept open in all rows of memory. When 4 bank SDRAM devices (64Mb technology) are used for a
particular row, up to 4 pages can be kept open within that row.
The DRAM interface of the 82443ZX is configured by the DRAM Control Register, DRAM
Timing Register, SDRAM Control Register, bits in the NBXCFG and the four DRAM Row
Boundary (DRB) Registers. The DRAM configuration registers noted above control the DRAM
interface to select EDO or SDRAM DRAMs, RAS timings, and CAS rates. The four DRB
Registers define the size of each row in the memory array, enabling the 82443ZX to assert the
proper CSA/B# pair for accesses to the array.
DRAM Organization and Configuration
The 82443ZX supports 64/72-bit DRAM configurations. In the following discussion the term row
refers to a set of memory devices that are simultaneously selected by a CSA/B# or RASA/B# pair.
The 82443ZX will support a maximum of 4 rows of memory when using SDRAMs in a desktop
configuration. Up to 4 rows of memory are supported when using EDO DRAM. A row may be
composed of discrete DRAM devices, single-sided or double-sided DIMMs.
4-14
82443ZX Host Bridge Datasheet