82443ZX Datasheet, PDF (105/116 Pages) Intel Corporation – Intel® 440ZX AGPset: Host Bridge/Controller

Functional Description
4.8.3
4.8.4
4.8.5
Clock Control Functions
The 82443ZX implements an independent Clock Gating power savings feature to reduce its own
average power consumption. The 82443ZX clock gating functions works along with the primary
PCI bus CLKRUN# function.
The Clock Gating function is enabled by setting the GCLKEN Configuration bit. This function
default value is 0. The AGP interface’s clock domain can be permanently disabled by the
AGP_DIS configuration bit. This allows further power savings in systems that AGP is not used.
CLKRUN Clocking States
There are three states in the CLKRUN# protocol:
• Clock Running: The clock is running and the bus is operational.
• Clock Stop Request: The central resource has indicated on the CLKRUN# line that
the clock is about to stop.
• Clock Stopped: The clock is stopped with CLKRUN# being monitored for a restart.
SDRAM Power Down Mode
The 82443ZX supports a SDRAM power down mode to minimize SDRAM power usage. The
82443ZX controls the SDRAM power mode per row, when all banks in a given row are idle, the
associated CKE signal is deasserted. When a powered down row address is requested, the
associated CKE is asserted.
SMRAM
SMRAM ranges
The 82443ZX supports the use of main memory as System Management RAM (SMRAM)
enabling the use of System Management Mode. There are two SMRAM options: Compatible
SMRAM (C_SMRAM) and Extended SMRAM (E_SMRAM). System Management RAM
(SMRAM) space provides a memory area that is available for the SMI handler's and code and data
storage. This memory resource is normally hidden from the operating system so that the processor
has immediate access to this memory space upon entry to SMM. 82443ZX provides three SMRAM
options:
• Below 1 MB option that supports compatible SMI handlers.
• Above 1 MB option that allows new SMI handlers to execute with write-back cacheable
SMRAM.
• Optional larger write-back cacheable T_SEG area from 128KB to 1MB in size above 1 MB
that is reserved from the highest area in system DRAM memory. The above 1 MB solutions
require changes to compatible SMRAM handlers code to properly execute above 1 MB.
Compatible SMRAM (C_SMRAM)
This is the traditional SMRAM feature supported in Intel AGPsets. When this function is enabled
via C_BASE_SEG[2:0]=010 and G_SMRAME=1 of the SMRAMC register, the 82443ZX
reserves 000A0000h through 000BFFFFh (A and B segments) of the main memory for use as non-
cacheable SMRAM.
82443ZX Host Bridge Datasheet
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