82443ZX Datasheet, PDF (53/116 Pages) Intel Corporation – Intel® 440ZX AGPset: Host Bridge/Controller

Register Description
3.3.23
3.3.24
RPS—SDRAM Row Page Size Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
74h–75h
0000h
Read/Write
16 bits
This register sets the row page size for SDRAM only. For EDO memory, the page size is fixed at
2 KB.
Bit
Description
Page Size (PS). Each pair of bits in this register indicate the page size used for one row of DRAM.
The encoding of the two bit fields.
Bits[1:0] Page Size
00
01
10
15:0 11
2 KB
4 KB
8 KB
Reserved
RPS bits Corresponding DRB register
1:0
DRB[0], row 0
3:2
DRB[1], row 1
5:4
DRB[2], row 2
7:6
DRB[3], row 3
9:15
Not Applicable in the 82443ZX.
SDRAMC—SDRAM Control Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
76h–77h
00h
Read/Write
16 bits
Bit
15:10
9:8
Description
Reserved
Idle/Pipeline DRAM Leadoff Timing (IPDLT). Adds a clock delay to the lead-off clock count
when bits 9:8 are set to 01. All other settings are illegal.
82443ZX Host Bridge Datasheet
3-29