82443ZX Datasheet, PDF (29/116 Pages) Intel Corporation – Intel® 440ZX AGPset: Host Bridge/Controller

Register Description
Figure 3-1. 82443ZX PCI Bus Hierarchy
CPU
82443ZX
Host Bridge
Host-to-PCI Bridge
Virtual Host-to-PCI Bridge
AGP Device
PCI Bus #1 – AGP
PCI Bus #0
3.2.1 Configuration Space Mechanism Overview
The 82443ZX supports two bus interfaces: PCI (referenced as Primary PCI) and AGP (referenced
as AGP). The AGP interface is treated as a second PCI bus from the configuration point of view.
The following sections describe the configuration space mapping mechanism associated with both
buses.
Note:
The configuration space for device #1 is controlled by the AGP_DIS bit in the PMCR register.
When the AGP_DIS bit (PMCR[1]) is set to 0, the configuration space for device #1 is enabled,
and the registers for device #1 are accessible through the configuration mechanism defined below.
When the AGP_DIS bit (PMCR[1]) is set to 1, the configuration space for device #1 is disabled.
All configuration cycles (reads and writes) to device #1 of bus 0 will cause the master abort status
bit for device #0/ bus 0 to be set. Configuration read cycles will return data of all 1’s. Configuration
write cycles will have no effect on the registers.
3.2.2
Routing the Configuration Accesses to PCI or AGP
Routing of configuration accesses to AGP is controlled via PCI-to-PCI bridge normal mechanism
using information contained within the PRIMARY BUS NUMBER, the SECONDARY BUS
NUMBER, and the SUBORDINATE BUS NUMBER registers of the Host-to-AGP internal
“virtual” PCI-to-PCI bridge device. Detailed description of the mechanism for translating CPU I/O
bus cycles to configuration cycles on one of the two buses is described below.
To distinguish between PCI configuration cycles targeting the two logical device register sets
supported in the 82443ZX, this document refers to the Host-to-PCI bridge PCI interface as PCI and
the Host- AGP PCI interface as AGP.
82443ZX Host Bridge Datasheet
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