82443ZX Datasheet, PDF (47/116 Pages) Intel Corporation – Intel® 440ZX AGPset: Host Bridge/Controller

Register Description
(DRB) Registers are programmed with an 8-bit upper address limit value. This upper address limit
is compared to bits [30:23] of the requested address, for each row, to determine if DRAM is being
targeted.
Note: DRAM is selected only if address[31:30] are zero.
Bit
Description
Row Boundary Address. This 8-bit value is compared against address lines A[30:23] to
7:0
determine the upper address limit of a particular row (i.e., DRB minus previous DRB = row size).
NOTE: When PCIRST# assertion occurs during POS/STR, these bits are not reset to ‘01h’.
Row Boundary Address
These 8 bit values represent the upper address limits of the four rows (i.e., this row minus previous
row = row size). Unpopulated rows have a value equal to the previous row (row size = 0). DRB3
reflects the maximum amount of DRAM in the system. The top of memory is determined by the
value written into DRB3.
Note: The 82443ZX supports a maximum of 256MB of DRAM.
As an example of a general purpose configuration where four physical rows are configured for
either single-sided or double-sided DIMMs, the memory array would be configured like the one
shown in Figure 3-2. In this configuration, the 82443ZX drives four CS# signals directly to the
DIMM rows. If single-sided DIMMs are populated, the even CS# signals are used and the odd
CS#s are not connected. If double-sided DIMMs are used, all four CS# signals are used per DIMM.
Figure 3-2. SDRAM DIMMs and Corresponding DRB Registers
CSA3#/CSB3#
CSA2#/CSB2#
CSA1#/CSB1#
CSA0#/CSB0#
DIMM1 – Back
DIMM1 – Front
DIMM0 – Back
DIMM0 – Front
DRB3
DRB2
DRB1
DRB0
82443ZX Host Bridge Datasheet
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