82443ZX Datasheet, PDF (8/116 Pages) Intel Corporation – Intel® 440ZX AGPset: Host Bridge/Controller

Figures
1-1 Intel^® 440ZX AGPset System Block Diagram...............................................1-2
3-1 82443ZX PCI Bus Hierarchy.........................................................................3-5
3-2 SDRAM DIMMs and Corresponding DRB Registers ..................................3-23
4-1 Memory System Address Space ..................................................................4-2
4-2 Typical Intel^® 440ZX AGPset System Clocking..........................................4-21
4-3 Reset CPURST# in a Desktop System When PCIRST# Asserted .............4-24
4-4 External Glue Logic Drives CPU Clock Ratio Straps ..................................4-24
5-1 82443ZX Pinout (Top View–left side) ...........................................................5-2
5-2 82443ZX Pinout (Top View–right side) .........................................................5-3
5-3 82443ZX BGA Package Dimensions—Top and Side Views ........................5-8
5-4 82443ZX BGA Package Dimensions—Bottom Views ..................................5-9
Tables
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Host Interface Signals...................................................................................2-1
Host Signals Not supported by the 82443ZX................................................2-3
DRAM Interface Signals ...............................................................................2-3
Primary PCI Interface Signals.......................................................................2-5
Primary PCI Sideband Interface Signals ......................................................2-6
AGP Interface Signals ..................................................................................2-7
Clocks, Reset, and Miscellaneous ................................................................2-9
Power Management Interface.......................................................................2-9
Reference Pins ...........................................................................................2-10
Strapping Options .......................................................................................2-11
82443ZX Register Map — Device 0 .............................................................3-8
Attribute Bit Assignment .............................................................................3-21
PAM Registers and Associated Memory Segments ...................................3-21
82443ZX Configuration Space—Device 1 ..................................................3-45
Memory Segments and their Attributes ........................................................4-3
SMRAM Decoding ........................................................................................4-7
SMRAM Range Decode ...............................................................................4-7
SMRAM Decode Control ..............................................................................4-7
Host Bus Transactions Supported By 82443ZX .........................................4-11
Host Responses supported by the 82443ZX ..............................................4-12
Host Special Cycles with 82443ZX .............................................................4-13
Sample Of Possible Mix And Match Options For 4 Row/2
DIMM Configurations ..................................................................................4-15
Data Bytes on DIMM Used for Programming DRAM Registers..................4-16
Supported Memory Configurations .............................................................4-17
MA Muxing vs. DRAM Address Split ..........................................................4-18
Programmable SDRAM Timing Parameters ...............................................4-18
EDO DRAM Timing Parameters .................................................................4-19
Low Power Mode ........................................................................................4-22
AGPset Reset .............................................................................................4-23
Reset Signals..............................................................................................4-23
82443ZX Alphabetical BGA Pin List .............................................................5-4
82443ZX Package Dimensions (492 BGA) ..................................................5-9
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82443ZX Host Bridge Datasheet