82443ZX Datasheet, PDF (48/116 Pages) Intel Corporation – Intel® 440ZX AGPset: Host Bridge/Controller

Register Description
3.3.19
The following 2 examples describe how the DRB Registers are programmed for cases of single-
sided and double-sided DIMMs on a motherboard.
Example #1 Single-sided DIMMs
Assume a total of 16 MB of DRAM are required using single-sided 1MB x 64 DIMMs. In this
configuration, two DIMMs are required.
DRB0 = 01h
DRB1 = 01h
DRB2 = 02h
DRB3 = 02h
populated (1 DIMM, 8 Mbyte this row)
empty row
populated (1 DIMM, 8 Mbyte this row)
empty row
Example #2 Mixed Single-/Double-sided DIMMs
As another example, consider a system that is initially shipped with 8 MB of memory using a 1M x
64 DIMM and that an additional 64MB of memory array is used to upgrade toa total of 72 MB of
memory. This can be handled by further populating the array with one 8M x 64 double-sided
DIMM (two rows), yielding a total of 72 MB of DRAM. The DRB Registers are programmed as
follows:
DRB0 = 01h
DRB1 = 01h
DRB2 = 05h
DRB3 = 09h
populated with 8 MB, 1MB x 64 single-sided DIMM
empty row
populated with 32 MB, 1/2 of 8M x 64 DIMM
populated with 32 MB, the other 1/2 of 8M x 64 DIMM
FDHC—Fixed DRAM Hole Control Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
68h
00h
Read/Write
8 bits
This 8-bit register controls 2 fixed DRAM holes: 512 KB – 640 KB and 15 MB –16 MB.
Bit
Description
Hole Enable (HEN). This field enables a memory hole in DRAM space. Host cycles matching an
enabled hole are passed on to PCI. PCI cycles matching an enabled hole will be ignored by the
82443ZX (no DEVSEL#). NOTE: A selected hole is not remapped.
7:6
00 = None
01 = 512 KB–640 KB (128 KB bytes)
10 = 15 MB – 16 MB (1 MB byte)
11 = Reserved
5:0
Reserved.
3-24
82443ZX Host Bridge Datasheet