82443ZX Datasheet, PDF (104/116 Pages) Intel Corporation – Intel® 440ZX AGPset: Host Bridge/Controller

Functional Description
4.8.2.1 CPU Reset
The CPU reset is generated by the 82443ZX in the following case:
• CPURST# is always asserted if PCIRST# is asserted.
• CPURST# is asserted during resume sequence from POS CRst_En= 1.
The 82443ZX deasserts CPURST# 1 ms after detecting the rising edge of PCIRST#. The
CPURST# is synchronous to host bus clock.
Figure 4-3. Reset CPURST# in a Desktop System When PCIRST# Asserted
HCLK
PCIRST#
PCLK
CPURST#
CRESET#
1m SEC
0 000 1 2
....
4.8.2.2 CPU Clock Ratio Straps
The Pentium II processors require their internal clock ratio to be set up via strapping pins
multiplexed onto signals A20M#, IGNE#, INTR, and NMI. These signals should reflect the
strapping values during the deasserted edge of CPURST# signal and be held stable for between 2 to
20 clocks. HCLKs after CPURST# is deasserted.
The 82443ZX is designed to support CPU strapping options with external logic, when PIIX4E is
used. Figure 4-4 illustrates the strapping pin timing when using the external glue logic (necessary
for PIIX4E). The external mux is switched via the CRESET# signal which is a 2 clock delayed
version of CPURST#.
Figure 4-4. External Glue Logic Drives CPU Clock Ratio Straps
12
HCLK
SUS_DIS strap
PCIRST#
PCLK
p_creset#
CRESET#
CPU straps
Suspend disable value latched when PCIRST#↑
0 01 2
....
1 ms
CPU strap values from external Glue Logic
33,333
4.8.2.3
82443ZX Straps
The 82443ZX strapping options are latched in the rising edge of PCIRST#.
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82443ZX Host Bridge Datasheet