6300ESB Datasheet, PDF (829/848 Pages) Intel Corporation – I/O Controller Hub

Testability
Table 734. XOR Chain #2
(RTCRST# asserted
for 5 PCI clocks
while PWROK active)
(Sheet 3 of 3)
Pin Name
Ball #
C/BE[1]#
AD[8]
AD[3]
IRDY#
PERR#
AD[14]
AD[12]
AD[10]
AD[23]
C/BE[2]#
DEVSEL#
AD[17]
AD[19]
AD[21]
AD[25]
AD[27]
AD[29]
AD[31]
OUTPUT FERR#
G7
H8
F5
E3
D2
D1
G6
E2
H7
F4
G5
E1
F2
K8
K7
F1
H4
G2
AA29
Table 735. XOR Chain #3
(RTCRST# asserted
for 6 PCI clocks
while PWROK active)
(Sheet 1 of 4)
Pin Name
IRQ[15]
VRMPWRGD
A20GATE
RCIN#
THRMTRIP#
FERR#
A20M#
INTR
NMI
IGNNE#
INIT#
Ball #
V23
Y26
AB29
V26
AA28
AA29
W27
Y28
Y29
U24
W28
Table 735. XOR Chain #3
(RTCRST# asserted
for 6 PCI clocks
while PWROK active)
(Sheet 2 of 4)
Pin Name
STPCLK#
SMI#
CPUSLP#
HL6
HL5
HL7
HL4
HLCOMP
HI_STB/HI_STBS
HI_STB#/HI_STBF
HL3
HL2
HL1
HL0
HL10
HL8
HL9
HL11
NC
NC
NC
NC
NC
CLK14
GPIO[32] / WDT
_TOUT#
SPKR
SATALED#
GPIO[40]
GPIO[18]
GPIO[19]
GPIO[20]
GPIO[21]
GPIO[23]
GPIO[42]
GPIO[38]
GPIO[43]
GPIO[41]
NC
Ball #
W29
V29
V28
T26
U28
R24
U29
T27
T28
T29
R28
R29
P28
P29
N28
N29
N25
M28
M29
L29
L28
M25
K29
L26
M24
K27
J28
H29
J27
L24
H28
K25
L22
G29
F29
K24
H26
G28
November 2007
Order Number: 300641-004US
Intel^® 6300ESB I/O Controller Hub
DS
829