6300ESB Datasheet, PDF (490/848 Pages) Intel Corporation – I/O Controller Hub

Intel^® 6300ESB ICH—11
11.1.6 Offset 0Bh: Base Class Code
Table 384. Offset 0Bh: Base Class Code
Device: 29
Offset: 0Bh
Default Value: 0Ch
Function: 7
Attribute: Read-Only
Size: 8-bit
Bits
7:0
Name
Base Class Code
Description
A value of 0Ch indicates that this is a Serial Bus controller.
Access
RO
11.1.7 Offset 0Dh: Master Latency Timer
Table 385. Offset 0Dh: Master Latency Timer
Device: 29
Offset: 0Dh
Default Value: 00h
Function: 7
Attribute: Read-Only
Size: 8-bit
Bits
7:0
Name
Master Latency Timer
Description
Since the USB EHCI controller is internally implemented with
arbitration through the Hub Interface (and not PCI), it does
not need a master latency timer. These bits will be fixed to 0.
Access
RO
11.1.8 Offset 10 - 13h: Memory Base Address
Table 386. Offset 10 - 13h: Memory Base Address
Device: 29
Offset: 10 - 13h
Default Value: 00000000h
Function: 7
Attribute: Read/Write
Size: 32-bit
Bits
Name
Description
31:1
0
Base Address
Bits [31:10] correspond to memory address signals [31:10],
respectively. This gives 1 Kbyte of locatable memory space
aligned to 1 Kbyte boundaries.
9:4
Reserved
Reserved.
3
Prefetchable
This bit is hardwired to 0, indicating that this range should
not be prefetched.
2:1
Type
This field is hardwired to 00b indicating that this range may
be mapped anywhere within 32-bit address space.
0
Resource Type Indicator This field is hardwired to 00b indicating that this range may
(RTE)
be mapped anywhere within 32-bit address space.
Access
RW
RO
RO
RO
Intel^® 6300ESB I/O Controller Hub
DS
490
November 2007
Order Number: 300641-004US