6300ESB Datasheet, PDF (309/848 Pages) Intel Corporation – I/O Controller Hub

7—Intel^® 6300ESB ICH
7.1.30 Offset 82h: PCI_MAST_STS—PCI Master Status
Register (HUB-PCI—D30:F0)
Table 176. Offset 82h: PCI_MAST_STS—PCI Master Status Register (HUB-PCI—
D30:F0)
Device: 30
Offset: 82h
Default Value: 00h
Function: 0
Attribute: Read/Write Clear
Size: 8-bit
Bits
Name
Description
Allows software to see if the internal DMA controller or LPC
Internal South PCI
has requested use of the PCI bus.
7
Master Request Status _{0 = Software clears this bit by writing a’1‘to the bit position.}
(INT_MREQ_STS)
1 = The Intel^® 6300ESB ICH’s internal DMA controller or LPC
has requested use of the PCI bus.
6:4
Reserved
Reserved.
Allows software to see if a particular bus master has
requested use of the PCI bus.
3:0
PCI Master Request _{0 = Software clears these bits by writing a 1 to the bit}
Status (PCI_MREQ_STS)
position.
1 = The associated PCI master has requested use of the PCI
bus.
Access
R/WC
R/WC
7.1.31 Offset 90h: ERR_CMD—Error Command Register
(HUB-PCI—D30:F0)
Note: This register configures the Intel^® 6300ESB ICH’s Device 30 responses to various
system errors. The actual assertion of the internal SERR# (routed to cause NMI# or
SMI#) is enabled through the PCI Command register.
Table 177. Offset 90h: ERR_CMD—Error Command Register (HUB-PCI—D30:F0)
Device: 30
Offset: 90h
Default Value: 00h
Lockable: No
Function: 0
Attribute: Read/Write
Size: 8-bit
Power Well: Core
Bits
7:3
2
1:0
Name
Reserved
SERR# Enable on
Receiving Target Abort
(SERR_RTA_EN)
Reserved
Description
Reserved.
0 = Disable.
1 = Enable. When SERR_EN is set, the Intel^® 6300ESB ICH
will report SERR# when SERR_RTA is set.
Reserved. Bit 1 was the SERR# Enabled for Delayed
Transaction Timeout, see Section 7.1.24, “Offset 3E - 3Fh:
BRIDGE_CNT—Bridge Control Register (HUB-PCI—D30:F0)”.
Access
R/W
November 2007
Order Number: 300641-004US
Intel^® 6300ESB I/O Controller Hub
DS
309