6300ESB Datasheet, PDF (539/848 Pages) Intel Corporation – I/O Controller Hub

12—Intel^® 6300ESB ICH
Table 441. Offset 02h: HST_CNT—Host Control Register (Sheet 3 of 3)
Device: 31
Offset: 02h
Default Value: 00h
Function: 3
Attribute: Read/Write
Size: 8-bit
Bits
1
0
Name
KILL
INTREN
Description
0 = Normal SMBus Host Controller functionality.
1 = When set, kills the current host transaction taking place,
sets the FAILED status bit, and asserts the interrupt (or
SMI#). This bit, once set, must be cleared by software to
allow the SMBus Host Controller to function normally.
0 = Disable.
1 = Enable the generation of an interrupt or SMI# upon the
completion of the command.
Access
R/W
R/W
12.2.3 Offset 03h: HST_CMD—Host Command Register
Table 442. Offset 03h: HST_CMD—Host Command Register
Device: 31
Offset: 03h
Default Value: 00h
Function: 3
Attribute: Read/Write
Size: 8-bit
Bits
7:0
Name
Description
This 8-bit field is transmitted by the host controller in the
command field of the SMBus protocol during the execution of
any command.
Access
R/W
12.2.4 Offset 04h: XMIT_SLVA—Transmit Slave Address
Register
Note: This register is transmitted by the host controller in the slave address field of the
SMBus protocol.
Table 443. Offset 04h: XMIT_SLVA—Transmit Slave Address Register
Device: 31
Offset: 04h
Default Value: 00h
Function: 3
Attribute: Read/Write
Size: 8-bit
Bits
Name
ADDRESS
RW
Description
7-bit address of the targeted slave.
Direction of the host transfer.
0 = Write
1 = Read
Access
R/W
R/W
November 2007
Order Number: 300641-004US
Intel^® 6300ESB I/O Controller Hub
DS
539