6300ESB Datasheet, PDF (41/848 Pages) Intel Corporation – I/O Controller Hub

Contents—Intel^® 6300ESB ICH
428 Offset 06 - 07h: STA—Device Status Register (SMBUS—D31:F3) .................................. 529
429 Offset 08h: RID—Revision ID Register (SMBUS—D31:F3) ............................................ 529
430 Offset 09h: PI—Programming Interface (SMBUS—D31:F3) .......................................... 530
431 Offset 0Ah: SCC—Sub Class Code Register (SMBUS—D31:F3)...................................... 530
432 Offset 0Bh: BCC—Base Class Code Register (SMBUS—D31:F3) .................................... 530
433 Offset 20 - 23h: SMB_BASE—SMBUS Base Address Register (SMBUS—D31:F3).............. 531
434 Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID (SMBUS—D31:F2/F4).......................... 531
435 Offset 2Eh - 2Fh: SID—Subsystem ID (SMBUS—D31:F2/F4) ........................................ 532
436 Offset 3Ch: INTR_LN—Interrupt Line Register (SMBUS—D31:F3).................................. 532
437 Offset 3Dh: INTR_PN—Interrupt Pin Register (SMBUS—D31:F3)................................... 532
438 Offset 40h: HOSTC—Host Configuration Register (SMBUS—D31:F3) ............................. 533
439 SMB I/O Registers.................................................................................................. 533
440 Offset 00h: HST_STS—Host Status Register .............................................................. 535
441 Offset 02h: HST_CNT—Host Control Register ............................................................. 537
442 Offset 03h: HST_CMD—Host Command Register ........................................................ 539
443 Offset 04h: XMIT_SLVA—Transmit Slave Address Register........................................... 539
444 Offset 05h: HST_D0—Data 0 Register ....................................................................... 540
445 Offset 06h: HST_D1—Data 1 Register ....................................................................... 540
446 Offset 07h: Host_BLOCK_DB—Host Block Data Byte Register ....................................... 541
447 Offset 08h: PEC—Packet Error Check Register............................................................ 542
448 Offset 09h: RCV_SLVA—Receive Slave Address Register.............................................. 542
449 Offset 0Ah: SLV_DATA—Receive Slave Data Register .................................................. 543
450 Offset 0Ch: AUX_STS—Auxiliary Status Register ........................................................ 543
451 Offset 0Dh: AUX_CTL—Auxiliary Control Register ....................................................... 544
452 Offset 0Eh: SMLINK_PIN_CTL—SMLink Pin Control Register ......................................... 544
453 Offset 0Fh: SMBUS_PIN_CTL—SMBUS Pin Control Register .......................................... 545
454 Offset 10h: SLV_STS—Slave Status Register ............................................................. 546
455 Offset 11H: SLV_CMD—Slave Command Register ....................................................... 546
456 Offset 14h: NOTIFY_DADDR—Notify Device Address ................................................... 547
457 Offset 16h: NOTIFY_DLOW—Notify Data Low Byte Register ......................................... 548
458 Offset 17h: NOTIFY_DHIGH—Notify Data High Byte Register........................................ 548
459 PCI Configuration Map (Audio—D31:F5) .................................................................... 549
460 Offset 00 - 01h: VID—Vendor Identification Register (Audio—D31:F5) .......................... 551
461 Offset 02 - 03h: DID—Device Identification Register (Audio—D31:F5) ........................... 551
462 Offset 04 - 05h: PCICMD—PCI Command Register (Audio—D31:F5).............................. 552
463 Offset 06 - 07h: PCISTS—PCI Device Status Register (Audio—D31:F5).......................... 553
464 Offset 08h: RID—Revision Identification Register (Audio—D31:F5) ............................... 554
465 Offset 09h: PI—Programming Interface Register (Audio—D31:F5) ................................ 554
466 Offset 0Ah: SCC—Sub Class Code Register (Audio—D31:F5) ........................................ 554
467 Offset 0Bh: BCC—Base Class Code Register (Audio—D31:F5)....................................... 555
468 Offset 0Eh: HEDT—Header Type Register (Audio—D31:F5) .......................................... 555
469 Offset 10 - 13h: NAMBAR—Native Audio Mixer Base Address Register (Audio—D31:F5) ... 556
470 Offset 14 - 17h: NABMBAR—Native Audio Bus Mastering Base Address Register (Audio—
D31:F5)557
471 Offset 18 - 1Bh: MMBAR—Mixer Base Address Register (Audio—D31:F5) ....................... 557
472 Offset 1C - 1Fh: MBBAR—Bus Master Base Address Register (Audio—D31:F5) ................ 558
473 Offset 2D - 2Ch: SVID—Subsystem Vendor ID Register (Audio—D31:F5)....................... 559
474 Offset 2E - 2Fh: SID—Subsystem ID Register (Audio—D31:F5) .................................... 559
475 Offset 34h: CAP_PTR—Capabilities Pointer (Audio—D31:F5)......................................... 560
476 Offset 3Ch: INTR_LN—Interrupt Line Register (Audio—D31:F5) .................................... 560
477 Offset 3Dh: INTR_PN—Interrupt Pin Register (Audio—D31:F5) ..................................... 561
478 Offset 40h: PCID—Programmable Codec ID Register (Audio—D31:F5)........................... 561
479 Offset 41h: CFG—Configuration Register (Audio—D31:F5) ........................................... 562
480 Offset 50h: PID—PCI Power Management Capability ID Register (Audio—D31:F5)........... 562
481 Offset 52h: PC—Power Management Capabilities Register (Audio—D31:F5).................... 563
November 2007
Order Number: 300641-004US
Intel^® 6300ESB I/O Controller Hub
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