6300ESB Datasheet, PDF (354/848 Pages) Intel Corporation – I/O Controller Hub

Intel^® 6300ESB ICH—8
8.2.9 DMA Master Clear Register
Table 228. DMA Master Clear Register
Device:
I/O Address:
Default Value:
31
Ch. #0-3 = 0Dh
Ch. #4-7 = DAh
xxxx xxxx
Function: 0
Attribute: Write-Only
Size: 8-bit
Bits
7:0
Name
Master Clear
Description
No specific pattern. Enabled with a write to the port. This has
the same effect as the hardware Reset. The Command,
Status, Request, and Byte Pointer flip/flop registers are
cleared and the Mask Register is set.
8.2.10 DMA_CLMSK—DMA Clear Mask Register
Table 229. DMA_CLMSK—DMA Clear Mask Register
Device:
I/O Address:
Default Value:
31
Ch. #0-3 = 0Eh;
Ch. #4-7 = DCh
xxxx xxxx
Lockable: No
Function: 0
Attribute: Write-Only
Size: 8-bit
Power Well: Core
Bits
7:0
Name
Clear Mask Register
Description
No specific pattern. Command enabled with a write to the
port.
Access
WO
Access
WO
Intel^® 6300ESB I/O Controller Hub
DS
354
November 2007
Order Number: 300641-004US