6300ESB Datasheet, PDF (414/848 Pages) Intel Corporation – I/O Controller Hub

Intel^® 6300ESB ICH—8
8.8.3.15 DEVTRAP_EN— Device Trap Enable Register
Note: This register enables the individual trap ranges to generate an SMI# when the
corresponding status bit in the DEVACT_STS register is set. When a range is enabled, I/
O cycles associated with that range will not be forwarded to LPC or IDE.
Note: Usage: Legacy only.
Table 298. DEVTRAP_EN— Device Trap Enable Register
Device: 31
I/O Address: PMBASE +48h
Default Value: 0000h
Lockable: No
Function: 0
Attribute: Read/Write
Size: 16-bit
Power Well: Core
Bits
15:1
4
13
12
11
10
9:6
5
4
3
Name
Reserved
ADLIB_TRP_EN
KBC_TRP_EN
MIDI_TRP_EN
AUDIO_TRP_EN
Reserved
LEG_IO_TRP_EN
Reserved
IDES1_TRP_EN
Description
Reserved.
Ad-Lib.
0 = Disable.
1 = Enable.
NOTE: This bit is no longer supported and will not be
validated.
KBC (60/64h).
0 = Disable.
1 = Enable.
MIDI.
0 = Disable.
1 = Enable.
NOTE: This bit is no longer supported and will not be
validated.
Audio (Sound Blaster “ORed” with MSS).
0 = Disable.
1 = Enable.
NOTE: This bit is no longer supported and will not be
validated.
Reserved.
Parallel Port, Serial Port 1, Serial Port 2, Floppy Disk
Controller.
0 = Disable.
1 = Enable.
Reserved.
IDE Secondary Drive 1.
0 = Disable.
1 = Enable.
Access
R/W
R/W
R/W
R/W
R/W
R/W
Intel^® 6300ESB I/O Controller Hub
DS
414
November 2007
Order Number: 300641-004US