6300ESB Datasheet, PDF (747/848 Pages) Intel Corporation – I/O Controller Hub

20—Intel^® 6300ESB ICH
20.1.15 Offset 2Eh - 2Fh: SID—Subsystem ID (SATA–
D31:F2)
Table 675. Offset 2Eh - 2Fh: SID—Subsystem ID (SATA–D31:F2)
Device: 31
Offset: 2Eh-2Fh
Default Value: 00h
Lockable: No
Function: 2
Attribute: Read/Write-Once
Size: 16-bit
Power Well: Core
Bits
15:0
Name
Subsystem ID (SID)
Description
The SID register, in combination with the SVID register,
enables the operating system (OS) to distinguish subsystems
from each other. Software (BIOS) sets the value in this
register. After that, the value may be read, but subsequent
writes to this register have no effect. The value written to this
register will also be readable through the corresponding SID
registers for the USB#1, USB#2 and SMBus functions.
Access
R/WO
20.1.16 Offset 34h: CAP—Capabilities Pointer Register
(SATA–D31:F2)
Table 676. Offset 34h: CAP—Capabilities Pointer Register (SATA–D31:F2)
Device: 31
Offset: 34h
Default Value: 80h
Function: 2
Attribute: Read-Only
Size: 8-bit
Bits
7:0
Name
Capability Pointer (CP)
Description
This bit indicates that the first capability pointer offset is 80h,
the MSI capability. This value will be 70h if the MAP register
(offset 90h) indicates that the SATA and IDE functions are
combined (values of 100, 101, 110, or 111).
Access
RO
20.1.17 Offset 3Ch: INTR_LN—Interrupt Line Register
(SATA–D31:F2)
Table 677. Offset 3Ch: INTR_LN—Interrupt Line Register (SATA–D31:F2)
Device: 31
Offset: 3Ch
Default Value: 00h
Function: 2
Attribute: Read/Write
Size: 8-bit
Bits
7:0
Name
Interrupt Line
Description
It is to communicate to software the interrupt line that the
interrupt pin is connected to.
Access
R/W
November 2007
Order Number: 300641-004US
Intel^® 6300ESB I/O Controller Hub
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