6300ESB Datasheet, PDF (303/848 Pages) Intel Corporation – I/O Controller Hub

7—Intel^® 6300ESB ICH
Table 170. Offset 3E - 3Fh: BRIDGE_CNT—Bridge Control Register (HUB-PCI—
D30:F0)
(Sheet 3 of 3)
Device: 30
Offset: 3E-3Fh
Default Value: 0000h
Function: 0
Attribute: Read/Write
Size: 16-bit
Bits
3
2
1
0
Name
VGA Enable
ISA Enable
SERR# Enable
Parity Error Response
Enable
Description
0 = No VGA device on PCI.
1 = Indicates that the VGA device is on PCI. Therefore, the
PCI to Hub Interface decoder will not accept memory
cycles in the range A0000h-BFFFFh. Note that the Intel^®
6300ESB ICH will never take I/O cycles in the VGA range
from PCI. If VGA is enabled on PCI-X Bridge Device 28
Function 0, offset 3Eh, bit 3. PCI-X will claim memory
cycles in the VGA range before the legacy PCI Bridge.
The Intel^® 6300ESB ICH ignores this bit. However, this bit is
read/write for software compatibility. Since the Intel^®
6300ESB ICH forwards all I/O cycles that are not in the USB,
AC’97, or IDE ranges to PCI, this bit would have no effect.
ISA should be enabled on the legacy PCI or the PCI/PCI-X
bridge, but NOT both. If both are enabled, unpredictable
results will occur.
0 = Disable
1 = When this bit is set AND bit 8 in CMD register (D30:F0
Offset 04h) is also set, the Intel^® 6300ESB ICH will set
the SSE bit in PD_STS register (D30:F0, offset 06h, bit
14) and also generate an NMI (or SMI# if NMI routed to
SMI) when the SERR# signal is asserted. The internal
SERR# will be generated only if the SERR_EN bit is also
set in offset 04h.
NOTE: See Section 5.1.4, “SERR# Functionality” for more
details on this bit.
0 = Disable
1 = Enable the Hub Interface to PCI bridge for parity error
detection and reporting on the PCI bus.
Access
R/W
R/W
R/W
R/W
November 2007
Order Number: 300641-004US
Intel^® 6300ESB I/O Controller Hub
DS
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