6300ESB Datasheet, PDF (126/848 Pages) Intel Corporation – I/O Controller Hub

Intel^® 6300ESB ICH—5
Table 47.
When the Intel^® 6300ESB ICH detects a bus idle condition on the APIC Bus, and it has
an interrupt to send over the APIC bus, it drives a start cycle to begin arbitration, by
driving bit 0 to a ‘0’ on an APICCLK rising edge. It then samples bit 1. When Bit 1 was a
zero, then a local APIC started arbitration for an EOI message on the same clock edge
that the Intel^® 6300ESB ICH started arbitration. The Intel^® 6300ESB ICH has thus lost
arbitration and will stop driving the APIC bus.
When the Intel^® 6300ESB ICH did not see an EOI message start, it will start
transferring its arbitration ID, located in bits [27:24] of its Arbitration ID register
(ARBID). Starting in Cycle 2, through Cycle 5, it will tri-state bit 0, and drive bit 1 to a
‘0’ when ARBID[27] is a ‘1’. When ARBID[27] is a ‘0’, it will also tri-state bit 1. At the
end of each cycle, the Intel^® 6300ESB ICH will sample the state of Bit 1 on the APIC
bus. When the Intel^® 6300ESB ICH did not drive Bit 1 (ARBID[27] = ‘0’), and it
samples a ‘0’, then another APIC agent started arbitration for the APIC bus at the same
time as the Intel^® 6300ESB ICH, and it has higher priority. The Intel^® 6300ESB ICH
will stop driving the APIC bus. Table 47 describes the arbitration cycles.
Arbitration Cycles
Cycle
Bit 1
1
EOI
2
NOT (ARBID[27])
3
NOT (ARBID[26])
4
NOT (ARBID[25])
5
NOT (ARBID[24])
Bit 0
0
1
1
1
1
Comment
Bit 1 = 1: Normal, Bit 1 = 0: EOI
Arbitration ID. When the Intel^® 6300ESB ICH samples
a different value than it sent, it lost arbitration.
5.7.5.2 Bus Message Formats
Table 48.
After bus arbitration, the winner is granted exclusive use of the bus and will drive its
message. APIC messages come in four formats, determined by the Delivery Mode bits.
These four messages are of different length, and are known by all APICs on the bus
through the transmission of the Delivery Mode bits:
APIC Message Formats
Message
EOI
Short
Lowest
Priority
Remote Read
# of
Cycles
14
21
33
39
Delivery
Mode Bits
Comments
End of Interrupt transmission from Local APIC to I/O
xxx
APIC on Level interrupts. EOI is known by the EOI
bit at the start of arbitration
001, 010, 100, I/O APIC delivery on Fixed, NMI, SMI, Reset, ExtINT,
101, 111
and Lowest Priority with focus processor messages
Transmission of Lowest Priority interrupts when the
001
status field indicates that the processor does not
have focus.
011
Message from one Local APIC to another to read
registers.
EOI Message for Level Triggered Interrupts
EOI messages are used by local APICs to send an EOI cycle occurring for a level
triggered interrupt to an I/O APIC. This message is needed so that the I/O APIC may
differentiate between a new interrupt on the interrupt line versus the same interrupt on
the interrupt line. The target of the EOI is given by the local APIC through the
transmission of the priority vector (V7 through V0) of the interrupt. Upon receiving this
Intel^® 6300ESB I/O Controller Hub
DS
126
November 2007
Order Number: 300641-004US