6300ESB Datasheet, PDF (516/848 Pages) Intel Corporation – I/O Controller Hub

Intel^® 6300ESB ICH—11
Table 416. Offset CAPLENGTH + 10 - 13h: CTRLDSSEGMENT—Control Data
Structure Segment Register
Device: 29
Offset: CAPLENGTH + 10-13h
Default Value: 00000000h
Function: 7
Attribute: Read/Write
Size: 32-bit
Bits
31:0
Name
Upper Address[63:32]
Description
This 32-bit field corresponds to address bits 63:32 when
forming a control data structure address.
Access
RW
11.2.2.6 Offset CAPLENGTH + 14 - 17h: PERIODICLISTBASE—
Periodic Frame
List Base Address
Note: This 32-bit register contains the beginning address of the Periodic Frame List in the
system memory. Since the Intel^® 6300ESB ICH host controller operates in 64-bit mode
(as indicated by the ‘1’ in the 64-bit Addressing Capability field in the HCCSPARAMS
register), then the most significant 32 bits of every control data structure address
comes from the CTRLDSSEGMENT register. HCD loads this register prior to starting the
schedule execution by the Host Controller. The memory structure referenced by this
physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this
register are combined with the Frame Index Register (FRINDEX) to enable the Host
Controller to step through the Periodic Frame List in sequence.
Table 417. Offset CAPLENGTH + 14 - 17h: PERIODICLISTBASE—Periodic Frame
List Base Address
Device: 29
Offset: CAPLENGTH + 14-17h
Default Value: 00000000h
Function: 7
Attribute: Read/Write
Size: 32-bit
Bits
31:1
2
11:0
Name
Base Address (Low)
Reserved
Description
These bits correspond to memory address signals [31:12],
respectively.
Reserved. Must be written as ‘0’s. During runtime, the value
of these bits are undefined.
Access
RW
11.2.2.7 Offset CAPLENGTH + 18 - 1Bh: ASYNCLISTADDR—Current
Asynchronous List Address
Note: This 32-bit register contains the address of the next asynchronous queue head to be
executed. Since the Intel^® 6300ESB ICH host controller operates in 64-bit mode (as
indicated by a ‘1’ in 64-bit Addressing Capability field in the HCCPARAMS register), then
the most significant 32 bits of every control data structure address comes from the
CTRLDSSEGMENT register. Bits [4:0] of this register cannot be modified by system
software and will always return ‘0’s when read. The memory structure referenced by
this physical memory pointer is assumed to be 32-byte aligned.
Intel^® 6300ESB I/O Controller Hub
DS
516
November 2007
Order Number: 300641-004US