6300ESB Datasheet, PDF (595/848 Pages) Intel Corporation – I/O Controller Hub

14—Intel^® 6300ESB ICH
14.2.1 x_BDBAR—Buffer Descriptor List Base Address
Register
Note: Software may read the register at offset 00h by performing a single 32-bit read from
address offset 00h. Reads across dWord boundaries are not supported.
Table 518. x_BDBAR—Buffer Descriptor List Base Address Register
Device: 29
I/O Address:
MBAR + 00h (MIBDBAR),
MBAR + 10h (MOBDBAR)
Default Value: 00000000h
Lockable: No
Function: 5
Attribute: Read/Write
Size: 32-bit
Power Well: Core
Bits
31:3
2:0
Name
Buffer Descriptor List
Base Address[31:3]
Description
These bits represent address bits 31:3. The entries should be
aligned on 8-byte boundaries.
Hardwired to ‘0’.
Access
R/W
14.2.2 x_CIV—Current Index Value Register
Note: Software may read the registers at offsets 04h, 05h and 06h simultaneously by
performing a single 32-bit read from address offset 04h. Software may also read this
register individually by doing a single 8-bit read to offset 04h. Reads across dWord
boundaries are not supported.
Table 519. x_CIV—Current Index Value Register
Device: 29
I/O Address:
MBAR + 04h (MICIV),
MBAR + 14h (MOCIV)
Default Value: 00h
Lockable: No
Function: 5
Attribute: Read-Only
Size: 8-bit
Power Well: Core
Bits
7:5
4:0
Name
Current Index Value
[4:0]
Description
Hardwired to ‘0’.
These bits represent which buffer descriptor within the list of
16 descriptors is being processed currently. As each
descriptor is processed, this value is incremented.
Access
RO
November 2007
Order Number: 300641-004US
Intel^® 6300ESB I/O Controller Hub
DS
595