6300ESB Datasheet, PDF (124/848 Pages) Intel Corporation – I/O Controller Hub

Intel^® 6300ESB ICH—5
5.7.5 APIC Bus Functional Description
Table 45. APIC Interrupt Mapping, APIC0 Agent
IRQ #
Via
SERIRQ
Direct
Via PCI
from pin message
Internal Modules
0
No
No
No
Cascade from 8259 #1
1
Yes
No
No²
2
No
No
No
8254 Counter 0, MMT #0 (legacy mode)
3
Yes
No
No²
4
Yes
No
No²
5
Yes
No
No²
6
Yes
No
No²
7
Yes
No
No²
8
No
No
No
RTC, MMT #1 (legacy mode)
9
Yes
No
No²
Option for SCI, TCO
10
Yes
No
No²
Option for SCI, TCO
11
Yes
No
No²
Option for SCI, TCO, MMT #2
12
Yes
No
No²
13
No
14
Yes
15
Yes
No
Yes¹
Yes¹
No
FERR# logic
No²
Storage (IDE/SATA) Primary (legacy mode)
No²
Storage (IDE/SATA) Secondary (legacy mode)
16 PIRQ[A]# PIRQ[A]#
No
USB1 UHCI Controller #1
17 PIRQ[B]# PIRQ[B]#
No
AC’97 Audio, Modem, option for SMbus
18 PIRQ[C]# PIRQ[C]#
No
Storage (IDE/SATA) native mode
19 PIRQ[D]# PIRQ[D]#
No
USB 1.0 UHCI Controller #2
20
N/A
PIRQ[E]#
No²
Option for SCI, TCO, MMT #0,1,2
21
N/A
PIRQ[F]#
No²
Option for SCI, TCO, MMT #0,1,2
22
N/A
PIRQ[G]#
No²
Option for SCI, TCO, MMT #0,1,2
23
N/A
PIRQ[H]#
No²
USB 2.0 EHCI Controller, option for SCI, TCO,
MMT #0,1,2
NOTES:
1. IRQ 14 and 15 may only be driven directly from the pins when in Legacy IDE mode.
2. NO from external devices, YES of access from processor
3. In APIC mode, the PCI interrupts A:H are mapped to IRQ[16:23].
4. When an interrupt is used for PCI IRQ[A:H], SCI, or TCO, it should not be used for ISA-style
interrupts (via SERIRQ)
5. When programming the polarity of internal interrupt sources on the APIC, interrupts 0
through 15 receive active-high internal interrupt sources; interrupts 16 through 23 receive
active-low internal interrupt sources
6. When IRQ11 is used for MMT #2, software should ensure IRQ 11 is not shared with any other
devices to ensure the proper operation of MMT #2. The Intel^® 6300ESB ICH does not prevent
sharing of IRQ 11.
7. PCI Message interrupts are not prevented by hardware in these cases. However, the system
must not program these interrupts as edge-triggered (as required for PCI message
interrupts) because the internal and external PIRQs on these inputs must be programmed in
level-triggered modes.
Intel^® 6300ESB I/O Controller Hub
DS
124
November 2007
Order Number: 300641-004US