6300ESB Datasheet, PDF (56/848 Pages) Intel Corporation – I/O Controller Hub

Intel^® 6300ESB ICH—3
Table 3.
Hub Interface Signals
HIREF
I
Hub Interface Voltage Reference. Analog input, expected
voltage 350mV
Hub Interface Voltage Swing: Analog input used to control the
voltage swing and impedance strength of Hub Interface pins.
Expected voltage is 800 mV.
HI_VSWING
I
NOTES:
1. Refer to the platform design guide for expected voltages.
2. Refer to the platform design guide for resistor values and routing
guidelines for each Hub Interface mode.
NOTES:
1. The Hub Interface signals are all in a separate power plane, called the Hub Interface plane.
2. During the S3, S4, and S5 states, power to the Hub Interface is assumed to be off. During S0
and S1 states, power to the Hub Interface must be on.
3.2 Firmware Hub Interface
Table 4.
Firmware Hub Interface Signals
Name
Type
Description
FWH[3:0] /
LAD[3:0]
FWH[4] /
LFRAME#
I/O
Firmware Hub Signals. Muxed with LPC address signals. Internal
pull-ups are provided.
I/O
Firmware Hub Signals. Muxed with LPC LFRAME# signal. LFRAME#:
Indicates the start of an LPC cycle, or an abort.
NOTE: All LPC/FWH signals are in the core well.
Intel^® 6300ESB I/O Controller Hub
DS
56
November 2007
Order Number: 300641-004US