6300ESB Datasheet, PDF (616/848 Pages) Intel Corporation – I/O Controller Hub

Intel^® 6300ESB ICH—16
16.2 Product Overview
Figure 29. WDT Block Diagram
PCI
PCI
Configuration
Registers
Preload Value 1
Preload Value 2
Down-Counter
Reset/Interrupt Control Logic
WDT_TOUT#
(External)
IRQ/SMI
(Internal)
The timer uses a 35-bit down-counter. The counter is loaded with the value from the
first Preload register. The timer is then enabled and starts counting down. The time at
which the WDT first starts counting down is called the first stage. When the host fails to
reload the WDT before the 35-bit down-counter reaches zero, the WDT generates an
internal interrupt. After the interrupt is generated, the WDT loads the value from the
second Preload register into the WDT’s 35-bit down-counter and starts counting down.
The WDT is now in the second stage. When the host still fails to reload the WDT before
the second timeout, the WDT drives the WDT_TOUT# pin low and sets the timeout bit
(WDT_TIMEOUT). This bit indicates that the System has become unstable. The
WDT_TOUT# pin is held low until the system is reset or the WDT times out again
(depending on TOUT_CNF). The process of reloading the WDT involves the following
sequence of writes:
1. Write 80 to offset BAR + 0Ch.
2. Write 86 to offset BAR + 0Ch.
3. Write 1 to WDT_RELOAD in Reload Register.
The same process is used for setting the values in the preload registers. The only
difference exists in step 3. Instead of writing a ‘1’ to the WDT_RELOAD, write the
desired preload value into the corresponding Preload register. This value is not loaded
into the 35-bit down-counter until the next time the WDT reenters the stage. For
example, when Preload Value 2 is changed, it is not loaded into the 35-bit down-
counter until the next time the WDT enters the second stage.
Intel^® 6300ESB I/O Controller Hub
DS
616
November 2007
Order Number: 300641-004US