6300ESB Datasheet, PDF (247/848 Pages) Intel Corporation – I/O Controller Hub

5—Intel^® 6300ESB ICH
Table 126. I²C Block Read Protocol (Sheet 2 of 2)
Bit
10
11-18
19
20
20-27
28
29
30-38
39
39-46
47
...
...
...
...
Description
Acknowledge from slave
Send DATA1 register
Acknowledge from slave
Repeated Start
Slave Address - 7 bits
Read
Acknowledge from slave
Data Byte 1 from slave - 8 bits
Acknowledge
Data Byte 2 from slave - 8 bits
Acknowledge
Data Bytes from slave/
Acknowledge
Data Byte N from slave - 8 bits
NOT Acknowledge
Stop
The Intel^® 6300ESB ICH will continue reading data from the peripheral until the NAK is received.
Block Write-Block Read Process Call
The Block Write-Block Read process call is a two-part message. The call begins with a
slave address and a write condition. After the command code the host issues a write
byte count (M) that describes how many more bytes will be written in the first part of
the message. If a master has 6 bytes to send, the byte count field will have the value 6
(0000 0110b), followed by the 6 bytes of data. The write byte count (M) cannot be
zero.
The second part of the message is a block of read data beginning with a repeated start
condition followed by the slave address and a Read bit. The next byte is the read byte
count (N), which may differ from the write byte count (M). The read byte count (N)
cannot be zero.
The combined data payload must not exceed 32 bytes. The byte length restrictions of
this process call are summarized as follows:
• M ≥ 1 byte
• N ≥ 1 byte
• M + N ≤ 32 bytes
The read byte count does not include the PEC byte. The PEC is computed on the total
message beginning with the first slave address and using the normal PEC
computational rules. It is highly recommended that a PEC byte be used with the Block
Write-Block Read Process Call. Software must do a read to the command register
(offset 2h) to reset the 32 byte buffer pointer prior to reading the block data register.
Note: There is no STOP condition before the repeated START condition, and a NACK signifies
the end of the read transfer.
Note: E32B bit in the Auxiliary Control register must be set when using this protocol.
November 2007
Order Number: 300641-004US
Intel^® 6300ESB I/O Controller Hub
DS
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