6300ESB Datasheet, PDF (755/848 Pages) Intel Corporation – I/O Controller Hub

20—Intel^® 6300ESB ICH
Table 683. Offset 54h: IDE_CONFIG—IDE I/O Configuration Register (SATA–
D31:F2) (Sheet 2 of 2)
Device: 31
Offset: 54h
Default Value: 00h
Function: 2
Attribute: Read-Write
Size: 32-bit
Bits
2
1
0
Name
Description
SCBO: Secondary Drive 0 = 33 MHz base clock for Ultra ATA timings.
0 Base Clock
1 = 66 MHz base clock for Ultra ATA timings
PCB1: Primary Drive 1 0 = 33 MHz base clock for Ultra ATA timings.
Base Clock
1 = 66 MHz base clock for Ultra ATA timings
PCB0: Primary Drive 0 0 = 33 MHz base clock for Ultra ATA timings.
Base Clock
1 = 66 MHz base clock for Ultra ATA timings
Access
R/W
R/W
R/W
20.1.25 Offset 70 - 71h: PID—PCI Power Management
Capability ID (SATA–D31:F2)
Table 684. Offset 70 - 71h: PID—PCI Power Management Capability ID (SATA–
D31:F2)
Device: 31
Offset: 70-71h
Default Value: 0001h
Function: 2
Attribute: Read-Only
Size: 16-bit
Bits
15:8
7:0
Name
Description
Next Capability (NEXT) Indicates that this is the last item in the list
Cap ID (CID)
Indicates that this pointer is a PCI power management.
Access
20.1.26 Offset 72 - 73h: PC—PCI Power Management
Capabilities (SATA–D31:F2)
Table 685. Offset 72 - 73h: PC—PCI Power Management Capabilities (SATA–
D31:F2)
Device: 31
Offset: 72-73h
Default Value: 0002
Function: 2
Attribute: Read-Only
Size: 16-bit
Bits
15:1
1
10
9
Name
PME_Support
D2_Support
D1_Support
Description
Indicates PME# cannot be generated form the SATA host
controller. When in low power state, resume events are not
allowed.
The D2 state is not supported
The D1 state is not supported
Access
November 2007
Order Number: 300641-004US
Intel^® 6300ESB I/O Controller Hub
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