HYS64D16301GU Datasheet, PDF (8/51 Pages) Infineon Technologies AG – 184-Pin Unbuffered Dual-In-Line Memory Modules

HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Pin Configuration
2
Pin Configuration
Table 4 Pin Definitions and Functions
Symbol
Type¹⁾
A0 - A12
I
BA0, BA1
I
DQ0 - DQ63
I/O
CB0 - CB7
I/O
RAS, CAS, WE
I
CKE0 - CKE1
I
DQS0 - DQS8
I/O
CK0 - CK2,
I
CK0 - CK2
I
DM0 - DM8
I
DQS9 - DQS17
I/O
S0, S1
I
V_DD
V_SS
V_DDQ
V_DDID
V_REF
V_DDSPD
SCL
PWR
GND
PWR
PWR
AI
PWR
I
SDA
I/O
SA0 - SA2
I
NC
NC
Function
Address Inputs
Bank Selects
Data Input/Output
Check Bits (× 72 organization only)
Command Inputs
Clock Enable
SDRAM low data strobes
SDRAM clock (positive lines)
SDRAM clock (negative lines)
SDRAM low data mask/
high data strobes
Chip Selects for Rank0 and Rank1
Power (+2.5 V)
Ground
I/O Driver power supply
VDD Indentification flag
I/O reference supply
Serial EEPROM power supply
Serial bus clock
Serial bus data line
slave address select
Not Connected
1) I: Input; O: Output; I/O: bidirectional In-/Output; AI: Analog Input; PWR: Power Supply; GND: Signal Ground; NC: Not
Connected
Note: S1 and CKE1 are used on two rank modules only
Data Sheet
8
V1.1, 2003-07