HYS64D16301GU Datasheet, PDF (26/51 Pages) Infineon Technologies AG – 184-Pin Unbuffered Dual-In-Line Memory Modules

HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
7) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on t_DQSS.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between V_OH(ac) and V_OL(ac).
11) CAS Latency 1.5 operation is supported on DDR200 devices only
12) t_RPRES is defined for CL = 1.5 operation only
13) For each of the terms, if not already an integer, round to the next highest integer. t_CK is equal to the actual system clock
cycle time.
14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 16 AC Timing - Absolute Specifications –6/–5
Parameter
Symbol
–6
DDR333
–5
Unit Note/
DDR400B
Test Condition ¹⁾
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock Half Period
Clock cycle time
t_AC
t_DQSCK
t_CH
t_CL
t_HP
t_CK
DQ and DM input hold time
t_DH
DQ and DM input setup time
t_DS
Control and Addr. input pulse width (each t_IPW
input)
DQ and DM input pulse width (each input) t_DIPW
Data-out high-impedance time from CK/CK t_HZ
Data-out low-impedance time from CK/CK t_LZ
Write command to 1^st DQS latching
transition
t_DQSS
DQS-DQ skew (DQS and associated DQ t_DQSQ
signals)
Data hold skew factor
t_QHS
DQ/DQS output hold time
DQS input low (high) pulse width (write
cycle)
t_QH
t_DQSL,H
Min. Max. Min. Max.
–0.7 +0.7 –0.6 +0.6 ns
–0.6 +0.6 –0.5 +0.5 ns
0.45 0.55 0.45 0.55 t_CK
0.45 0.55 0.45 0.55 t_CK
min. (t_CL, t_CH) min. (t_CL, t_CH) ns
6
12 5
12 ns
6
12 6
12 ns
7.5 12 7.5 12 ns
0.45 —
0.4 —
ns
0.45 —
0.4 —
ns
2.2 —
tbd —
ns
1.75 —
tbd —
ns
–0.7 +0.7 –0.6 +0.6 ns
–0.7 +0.7 –0.6 +0.6 ns
0.75 1.25 0.75 1.25 t_CK
—
—
—
—
t_HP –
t_QHS
0.35
+0.40
+0.45
+0.50
+0.55
—
—
—
—
—
—
t_HP –
t_QHS
0.35
+0.40 ns
+0.40 ns
+0.50 ns
+0.50 ns
—
ns
—
t_CK
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
CL = 3.0 ^2)3)4)5)
CL = 2.5 ^2)3)4)5)
CL = 2.0 ^2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)6)
2)3)4)5)6)
2)3)4)5)7)
2)3)4)5)7)
2)3)4)5)
TFBGA ^2)3)4)5)
TSOPII ^2)3)4)5)
TFBGA ^2)3)4)5)
TSOPII ^2)3)4)5)
2)3)4)5)
2)3)4)5)
Data Sheet
26
V1.1, 2003-07