HYS64D16301GU Datasheet, PDF (36/51 Pages) Infineon Technologies AG – 184-Pin Unbuffered Dual-In-Line Memory Modules

HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 19 SPD Codes for PC2100 Modules “–7F” (cont’d)
Byte
23
24
25
26
27
28
29
30
31
32
33
34
35
36 to 40
41
42
43
44
45
Description
Min. Clock Cycle Time at
CAS Latency = 2
7.5 ns
Access Time from Clock for 0.75 ns
CL = 2
Minimum Clock Cycle Time not supported
for CL = 1.5
Access Time from Clock at not supported
CL = 1.5
Minimum Row Precharge
Time
15 ns
Minimum Row Act. to Row
Act. Delay t_RRD
Minimum RAS to CAS Delay
t_RCD
Minimum RAS Pulse Width
t_RAS
Module Bank Density (per
Bank)
15 ns
15 ns
45 ns
128 MByte/256 MByte
Addr. and Command Setup 0.9 ns
Time
Addr. and Command Hold 0.9 ns
Time
Data Input Setup Time
0.5 ns
Data Input Hold Time
0.5 ns
Superset Information
–
Minimum Core Cycle Time 60 ns
t_RC
Min. Auto Refresh Cmd Cycle 75 ns
Time t_FRC
Maximum Clock Cycle Time 12 ns
t_CK
Max. DQS-DQ Skew t_DQSQ 0.5 ns
X-Factor tQHS
0.75 ns
Data Sheet
36
256MB
× 72
1 rank
HEX
75
75
00
00
3C
3C
3C
2D
40
90
90
50
50
00
3C
4B
30
32
75
512MB
× 72
1 rank
HEX
75
75
00
00
3C
3C
3C
2D
40
90
90
50
50
00
3C
4B
30
32
75
V1.1, 2003-07