HYS64D16301GU Datasheet, PDF (25/51 Pages) Infineon Technologies AG – 184-Pin Unbuffered Dual-In-Line Memory Modules

HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 15 AC Timing - Absolute Specifications –8/–7/–7F (cont’d)
Parameter
Symbol
–8
–7
–7F
DDR200
DDR266A
DDR266
Min. Max. Min. Max. Min. Max.
Address and control input t_IS
setup time
1.1 —
0.9 —
0.9 —
1.1 —
1.0 —
1.0 —
Unit Note/
Test Condition ¹⁾
ns fast slew rate
3)4)5)6)10)
ns slow slew rate
3)4)5)6)10)
Address and control input t_IH
hold time
1.1 —
1.1 —
0.9 —
1.0 —
0.9 —
1.0 —
ns fast slew rate
3)4)5)6)10)
ns slow slew rate
3)4)5)6)10)
Read preamble
t_RPRE
0.9
1.1
0.9
1.1
0.9
1.1
t_CK CL > 1.5 ^2)3)4)5)
t_RPRE1.5 0.9
1.1
NA
NA
t_CK CL = 1.5 ^2)3)4)5)11)
Read preamble setup time t_RPRES 1.5 —
NA
NA
ns
2)3)4)5)12)
Read postamble
t_RPST
0.40 0.60 0.40 0.60 0.40 0.60 t_CK ^2)3)4)5)
Active to Precharge
command
t_RAS
50
120 45
120 45
120
ns
2)3)4)5)
E+3
E+3
E+3
Active to Active/Auto-
t_RC
refresh command period
70
—
65
—
60
—
ns
2)3)4)5)
Auto-refresh to Active/Auto- t_RFC
80
—
75
—
75
—
ns
2)3)4)5)
refresh command period
Active to Read or Write
t_RCD
20
—
20
—
15
—
ns
2)3)4)5)
delay
Precharge command period t_RP
20
—
20
—
15
—
ns
2)3)4)5)
Active to Autoprecharge t_RAP
20
—
20
—
15
—
ns
2)3)4)5)
delay
Active bank A to Active
t_RRD
15
—
15
—
15
—
ns
2)3)4)5)
bank B command
Write recovery time
t_WR
Auto precharge write
t_DAL
recovery + precharge time
15
—
15
—
15
—
(t_wr/t_CK) + (t_rp/t_CK)
ns
2)3)4)5)
t_CK
2)3)4)5)13)
Internal write to read
t_WTR
1
—1
—
1
—
t_CK CL > 1.5 ^2)3)4)5)
command delay
t_WTR1.5 2
—
—
—
—
—
t_CK CL = 1.5 ^2)3)4)5)
Exit self-refresh to non-read t_XSNR 80
—
75
—
75
—
ns
2)3)4)5)
command
Exit self-refresh to read
command
t_XSRD
200 —
200 —
200 —
t_CK
2)3)4)5)
Average Periodic Refresh t_REFI
—
7.8 —
7.8 —
7.8
µs
2)3)4)5)14)
Interval
1) 0 ° C ≤T_A ≤70 ° C; V_DDQ = 2.5 V ± 0.2 V, V_DD = +2.5 V ± 0.2 V
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333, DDR266, and = 1 V/ns for DDR200
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until V_REF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
Data Sheet
25
V1.1, 2003-07