HYS64D16301GU Datasheet, PDF (31/51 Pages) Infineon Technologies AG – 184-Pin Unbuffered Dual-In-Line Memory Modules

HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 17 Operating, Standby and Refresh Currents (PC1600, –8) (cont’d)
Byte
Description
34
Data Input Setup Time 0.6 ns
35
Data Input Hold Time 0.6 ns
36 to 40 Superset Information –
41
Minimum Core Cycle 70 ns
Time t_RC
42
Min. Auto Refresh 80 ns
Cmd Cycle Time t_FRC
43
Maximum Clock Cycle 12 ns
Time t_CK
44
Max. DQS-DQ Skew 0.6 ns
t_DQSQ
45
X-Factor tQHS
1.0 ns
46 to 61 Superset Information –
62
SPD Revision
Revision 0.0
63
Checksum for Bytes 0 –
- 62
64
Manufacturers
–
JEDEC ID Codes
65 to 71 Manufacturer
–
72
Module Assembly –
Location
73 to 90 Module Part Number –
91 to 92 Module
Code
Revision –
93 to 94 Module
–
Manufacturing Date
95 to 98 Module Serial Number –
99 to 127 –
–
128 to 255 open for Customer –
use
128MB
× 64
1 rank
HEX
60
60
00
46
256MB
× 64
1 rank
HEX
60
60
00
46
256MB
× 72
1 rank
HEX
60
60
00
46
512MB
× 64
2 ranks
HEX
60
60
00
46
512MB
× 72
2 ranks
HEX
60
60
00
46
50
50
50
48
50
30
30
30
30
30
3C
3C
3C
3C
3C
A0
A0
A0
A0
A0
00
00
00
00
00
00
00
00
00
00
E8
A7
B9
A8
B9
C1
C1
C1
C1
C1
Infineon Infineon Infineon Infineon Infineon
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Data Sheet
31
V1.1, 2003-07