HYS64D16301GU Datasheet, PDF (18/51 Pages) Infineon Technologies AG – 184-Pin Unbuffered Dual-In-Line Memory Modules

HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 9 DC Operating Conditions (SSTL_2 Inputs)
Parameter
Symbol
Values
Unit Note/ Test Condition ¹⁾
DC Input Logic High
DC Input Logic Low
Input Leakage Current
Output Leakage Current
V_{IH (DC)}
V_{IL (DC)}
I_IL
I_OL
min.
max.
V_REF + 0.15 V_DDQ + 0.3
V
2)
– 0.30
–5
V_REF – 0.15 V
–
5
µA
3)
–5
5
µA
3)
1) V_DDQ = 2.5 V, T_A = 70 ° C, Voltage Referenced to V_SS
2) The relationship between the V_DDQ of the driving device and the V_REF of the receiving device is what determines noise
margins. However, in the case of V_{IH (max.)} (input overdrive), it is the V_DDQ of the receiving device that is referenced. In the
case where a device is implemented such that it supports SSTL_2 inputs but has no SSTL_2 outputs (such as a translator),
and therefore no V_DDQ supply voltage connection, inputs must tolerate input overdrive to 3.0 V (High corner
V_DDQ + 300 mV).
3) For any pin under test input of 0 V ≤VIN ≤V_DDQ + 0.3 V. Values are shown per DDR SDRAM component
Data Sheet
18
V1.1, 2003-07