HYS64D16301GU Datasheet, PDF (35/51 Pages) Infineon Technologies AG – 184-Pin Unbuffered Dual-In-Line Memory Modules

HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 19 SPD Codes for PC2100 Modules “–7F”
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Description
Number of SPD Bytes
128
Total Bytes in Serial PD
256
Memory Type
DDR-SDRAM
Number of Row Addresses 13
Number of Column
9/10
Addresses
Number of DIMM Banks
1/2
Module Data Width
× 64/× 72
Module Data Width (cont’d) 0
Module Interface Levels
SSTL_2.5
SDRAM Cycle Time at
7 ns
CL = 2.5
Access Time from Clock at 0.75 ns
CL = 2.5
DIMM config
non-ECC/ECC
Refresh Rate/Type
Self-Refresh 7.8 µs
SDRAM Width, Primary
× 16/ × 8
Error Checking SDRAM Data na/ × 8
Witdh
Minimum Clock Delay for
Back-to-Back Random
Column Address
t_CCD = 1 CLK
Burst Length Supported
2, 4 & 8
Number of SDRAM Banks 4
Supported CAS Latencies CAS latency = 2 & 2.5
CS Latencies
CS latency = 0
WE Latencies
Write latency = 1
SDRAM DIMM Module
Attributes
unbuffered
SDRAM Device Attributes: −
General
256MB
× 72
1 rank
HEX
80
08
07
0D
0A
01
48
00
04
70
75
02
82
08
08
01
0E
04
0C
01
02
20
C0
Data Sheet
35
512MB
× 72
1 rank
HEX
80
08
07
0D
0A
02
48
00
04
70
75
02
82
08
08
01
0E
04
0C
01
02
20
C0
V1.1, 2003-07