HYS64D16301GU Datasheet, PDF (27/51 Pages) Infineon Technologies AG – 184-Pin Unbuffered Dual-In-Line Memory Modules

HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 16 AC Timing - Absolute Specifications –6/–5 (cont’d)
Parameter
Symbol
–6
DDR333
Min. Max.
DQS falling edge to CK setup time (write t_DSS
cycle)
0.2 —
DQS falling edge hold time from CK (write t_DSH
cycle)
0.2 —
Mode register set command cycle time
Write preamble setup time
Write postamble
Write preamble
Address and control input setup time
t_MRD
t_WPRES
t_WPST
t_WPRE
t_IS
2
0
0.40
0.25
0.75
—
—
0.60
—
—
–5
DDR400B
Min. Max.
0.2 —
0.2 —
2
—
0
—
0.40 0.60
0.25 —
0.6 —
Unit Note/
Test Condition ¹⁾
t_CK
2)3)4)5)
t_CK
2)3)4)5)
t_CK
2)3)4)5)
ns
2)3)4)5)8)
t_CK
2)3)4)5)9)
t_CK
2)3)4)5)
ns fast slew rate
3)4)5)6)10)
0.8 —
NA
ns slow slew rate
3)4)5)6)10)
Address and control input hold time
t_IH
0.75 —
0.6 —
ns fast slew rate
3)4)5)6)10)
0.8 —
NA
ns slow slew rate
3)4)5)6)10)
Read preamble
Read postamble
Active to Precharge command
Active to Active/Auto-refresh command
period
t_RPRE
t_RPST
t_RAS
t_RC
0.9
0.40
42
60
1.1 0.9
0.60 0.40
70E+3 40
—
55
1.1
t_CK
0.60 t_CK
70E+3 ns
—
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Auto-refresh to Active/Auto-refresh
command period
t_RFC
72 —
65
—
ns
2)3)4)5)
Active to Read or Write delay
t_RCD
18
—
15
—
ns
2)3)4)5)
Precharge command period
t_RP
18
—
15
—
ns
2)3)4)5)
Active to Autoprecharge delay
t_RAP
18 —
15
—
ns
2)3)4)5)
Active bank A to Active bank B command t_RRD
12
—
10
—
ns
2)3)4)5)
Write recovery time
t_WR
15
—
15
—
ns
2)3)4)5)
Auto precharge write recovery + precharge t_DAL
time
t_CK
2)3)4)5)11)
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
t_WTR
t_XSNR
t_XSRD
t_REFI
1
—
75 —
200 —
—
7.8
1
—
75 —
200 —
—
7.8
t_CK
2)3)4)5)
ns
2)3)4)5)
t_CK
2)3)4)5)
µs
2)3)4)5)12)
1) 0 ° C ≤T_A ≤70 ° C; V_DDQ = 2.5 V ±0.2 V, V_DD = +2.5 V ±0.2 V (DDR333); V_DDQ = 2.6 V ±0.1 V, V_DD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until V_REF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
Data Sheet
27
V1.1, 2003-07