HYS64D16301GU Datasheet, PDF (39/51 Pages) Infineon Technologies AG – 184-Pin Unbuffered Dual-In-Line Memory Modules

HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 20 SPD Codes for PC2700 Modules “–6” (cont’d)
Byte
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
128MB
× 64
1 rank
Description
HEX
Supported CAS
Latencies
CAS latency = 2 & 2.5 0C
CS Latencies
CS latency = 0
01
WE Latencies
Write latency = 1
02
SDRAM DIMM Module unbuffered
20
Attributes
SDRAM Device
−
C0
Attributes: General
Min. Clock Cycle Time 7.5 ns
75
at CAS Latency = 2
Access Time from
0.70 ns
70
Clock for
CL = 2
Minimum Clock Cycle not supported
00
Time for CL = 1.5
Access Time from
not supported
00
Clock at
CL = 1.5
Minimum Row
18 ns
48
Precharge Time
Minimum Row Act. to 12 ns
30
Row Act. Delay t_RRD
Minimum RAS to CAS 18 ns
48
Delay t_RCD
Minimum RAS Pulse 42 ns
2A
Width t_RAS
Module Bank Density 128 MByte/256 MByte 20
(per Bank)
Addr. and Command 0.75 ns
75
Setup Time
Addr. and Command 0.75 ns
75
Hold Time
Data Input Setup Time 0.45 ns
45
Data Input Hold Time 0.45 ns
45
256MB
× 64
1 rank
HEX
0C
01
02
20
C0
75
70
00
00
48
30
48
2A
40
75
75
45
45
256MB
× 72
1 rank
HEX
0C
01
02
20
C0
75
70
00
00
48
30
48
2A
40
75
75
45
45
512MB
× 64
2 ranks
HEX
0C
512MB
× 72
2 ranks
HEX
0C
01
01
02
02
20
20
C0
C0
75
75
70
70
00
00
00
00
48
48
30
30
48
48
2A
2A
40
40
75
75
75
75
45
45
45
45
Data Sheet
39
V1.1, 2003-07