HYS64D16301GU Datasheet, PDF (34/51 Pages) Infineon Technologies AG – 184-Pin Unbuffered Dual-In-Line Memory Modules

HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 18 SPD Codes for PC2100 Modules “–7” (cont’d)
Byte
Description
36 to 40 Superset Information –
41
Minimum Core Cycle 65 ns
Time t_RC
42
Min. Auto Refresh 75 ns
Cmd Cycle Time t_FRC
43
Maximum Clock Cycle 12 ns
Time t_CK
44
Max. DQS-DQ Skew 0.5 ns
t_DQSQ
45
X-Factor tQHS
0.75 ns
46 to 61 Superset Information –
62
SPD Revision
Revision 0.0
63
Checksum for Bytes 0 –
- 62
64
Manufacturers
–
JEDEC ID Codes
65 to 71 Manufacturer
–
72
Module Assembly –
Location
73 to 90 Module Part Number –
91 to 92 Module
Code
Revision –
93 to 94 Module Manufacturing –
Date
95 to 98 Module Serial Number –
99 to 127 –
–
128 to 255 open for Customer –
use
128MB
× 64
1 rank
HEX
00
41
256MB
× 64
1 rank
HEX
00
41
256MB
× 72
1 rank
HEX
00
41
512MB
× 64
2 ranks
HEX
00
41
512MB
× 72
2 ranks
HEX
00
41
4B
4B
4B
4B
4B
30
30
30
30
30
32
32
32
32
32
75
75
75
75
75
00
00
00
00
00
00
00
00
00
00
99
B2
C4
B3
C4
C1
C1
C1
C1
C1
Infineon Infineon Infineon Infineon Infineon
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–
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–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
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Data Sheet
34
V1.1, 2003-07