HYS64D16301GU Datasheet, PDF (19/51 Pages) Infineon Technologies AG – 184-Pin Unbuffered Dual-In-Line Memory Modules

HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3.2
Current Conditions and Specification
Table 10 I_DD Conditions
Parameter
Operating Current 0
one bank; active/ precharge; t_RC = t_RC,MIN;
DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤V_IL,MAX
Precharge Floating Standby Current
CS ≥ V_IH,,MIN, all banks idle; CKE ≥ V_IH,MIN;
address and other control inputs changing once per clock cycle; V_IN = V_REF for DQ, DQS and DM.
Precharge Quiet Standby Current
CS ≥ V_IHMIN, all banks idle; CKE ≥ V_IH,MIN;
address and other control inputs stable at ≥ V_IH,MIN or ≤V_IL,MAX; V_IN = V_REF for DQ, DQS and DM.
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤V_ILMAX; V_IN = V_REF for DQ, DQS and DM.
Active Standby Current
one bank active; CS ≥ V_IH,MIN; CKE ≥ V_IH,MIN; t_RC = t_RAS,MAX;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; I_OUT = 0 mA
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
Auto-Refresh Current
t_RC = t_RFCMIN, distributed refresh
Self-Refresh Current
CKE ≤0.2 V; external clock on
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
Symbol
I_DD0
I_DD1
I_DD2P
I_DD2F
I_DD2Q
I_DD3P
I_DD3N
I_DD4R
I_DD4W
I_DD5
I_DD6
I_DD7
Data Sheet
19
V1.1, 2003-07