HYS64D16301GU Datasheet, PDF (41/51 Pages) Infineon Technologies AG – 184-Pin Unbuffered Dual-In-Line Memory Modules

HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 21 SPD Codes for PC3200 Modules “–5”
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
128MB 256MB 256MB 512MB 512MB
× 64 × 64 × 72 × 64 × 72
1 rank 1 rank 1 rank 2 ranks 2 ranks
Description
HEX HEX HEX HEX HEX
Programmed SPD Bytes in E2PROM 128
80
80
80
80
80
Total number of Bytes in E2PROM
256
08
08
08
08
08
Memory Type DDR-I = 07h
DDR-SDRAM 07
07
07
07
07
# of Row Addresses
13
0D
0D
0D
0D
0D
# Number of Column Addresses
9/10
09
0A
0A
0A
0A
# of DIMM Banks
1/2
01
01
01
02
02
Data Width (LSB)
× 64/× 72
40
40
48
40
48
Data Width (MSB)
0
00
00
00
00
00
Interface Voltage Levels
SSTL_2.5
04
04
04
04
04
tCK @ CLmax (Byte 18) [ns]
5 ns
50
50
50
50
50
tAC SDRAM @ CLmax (Byte 18) [ns] 0.50 ns
50
50
50
50
50
DIMM Configuration Type (non- / ECC) non-ECC/ECC 00
00
02
00
02
Refresh Rate
Self-Refresh
82
82
82
82
82
7.8 µs
Primary SDRAM width
× 16/ × 8
10
08
08
08
08
Error Checking SDRAM width
na/ × 8
00
00
08
00
08
tCCD [cycles]
Burst Length Supported
t_CCD = 1 CLK
01
01
01
01
01
2, 4 & 8
0E
0E
0E
0E
0E
Number of Banks on SDRAM
4
04
04
04
04
04
CAS Latency
CAS latency = 2, 1C
1C
1C
1C
1C
2.5, 3
CS Latency
CS latency = 0 01
01
01
01
01
WE (Write) Latency
Write latency = 1 02
02
02
02
02
DIMM Attributes
unbuffered
20
20
20
20
20
Component Attributes
−
C1
C1
C1
C1
C1
tCK @ CLmax -0.5 (Byte 18) [ns]
6.0 ns
60
60
60
60
60
tAC SDRAM @ CLmax -0.5 [ns]
0.50 ns
50
50
50
50
50
tCK @ CLmax -1 (Byte 18) [ns]
7.5 ns
75
75
75
75
75
tAC SDRAM @ CLmax -1 [ns]
not supported 50
50
50
50
50
tRPmin (ns)
15 ns
3C
3C
3C
3C
3C
tRRDmin [ns]
10 ns
28
28
28
28
28
Data Sheet
41
V1.1, 2003-07