HYS64D16301GU Datasheet, PDF (16/51 Pages) Infineon Technologies AG – 184-Pin Unbuffered Dual-In-Line Memory Modules

HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Pin Configuration
6 DRAM Loads
CK R = 120 Ω ± 5%
DIMM
Connector
CK
DRAM1
DRAM2
DRAM3
DRAM4
DRAM5
DRAM6
3 DRAM Loads
R = 120 Ω ± 5%
DIMM
Connector
DRAM1
Cap.
DRAM3
Cap.
DRAM5
Cap.
1 DRAM Loads
Cap.
R = 120 Ω ± 5%
DIMM
Connector
Cap.
DRAM3
Cap.
Cap.
Cap.
Cap. = 1/2 DDR SDRAM input capacitance; 1.0 pF ± 20%
Figure 6 Clock Net Wiring
4 DRAM Loads
R = 120 Ω ± 5%
DIMM
Connector
2 DRAM Loads
R = 120 Ω ± 5%
DIMM
Connector
DRAM1
DRAM2
Cap.
Cap.
DRAM5
DRAM6
DRAM1
Cap.
Cap.
Cap.
DRAM5
Cap.
Data Sheet
16
V1.1, 2003-07