HYS64D16301GU Datasheet, PDF (29/51 Pages) Infineon Technologies AG – 184-Pin Unbuffered Dual-In-Line Memory Modules

HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
4
SPD Contents
Table 17 Operating, Standby and Refresh Currents (PC1600, –8)
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
Number of SPD Bytes 128
Total Bytes in Serial 256
PD
Memory Type
DDR-SDRAM
Number of Row
13
Addresses
Number of Column 9/10
Addresses
Number of DIMM
1/2
Banks
Module Data Width × 64/× 72
Module Data Width 0
(cont’d)
Module Interface
Levels
SSTL_2.5
SDRAM Cycle Time at 8 ns
CL = 2.5
Access Time from
Clock at
CL = 2.5
0.8 ns
DIMM config
non-ECC/ECC
Refresh Rate/Type Self-Refresh 7.8 µs
SDRAM Width,
Primary
× 16/ × 8
Error Checking
na/ × 8
SDRAM Data Witdh
Minimum Clock Delay
for Back-to-Back
Random Column
Address
t_CCD = 1 CLK
Burst Length
Supported
2, 4 & 8
128MB
× 64
1 rank
HEX
80
08
256MB
× 64
1 rank
HEX
80
08
256MB
× 72
1 rank
HEX
80
08
512MB
× 64
2 ranks
HEX
80
08
512MB
× 72
2 ranks
HEX
80
08
07
07
07
07
07
0D
0D
0D
0D
0D
09
0A
0A
0A
0A
01
01
01
02
01
40
40
48
40
48
00
00
00
00
00
04
04
04
04
04
80
80
80
80
80
80
80
80
80
80
00
00
02
00
02
82
82
82
82
82
10
08
08
08
08
00
00
08
00
08
01
01
01
01
01
0E
0E
0E
0E
0E
Data Sheet
29
V1.1, 2003-07