HYB25D256400B Datasheet, PDF (63/83 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM

HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Electrical Characteristics
Table 19 AC Timing - Absolute Specifications for DDR333 and DDR400B
Parameter
Symbol
–6
DDR333
–5
DDR400B
Unit
Note/ Test
Condition ¹⁾
Min. Max. Min. Max.
Exit self-refresh to read command
Average Periodic Refresh Interval
t_XSRD
t_REFI
200 —
—
7.8
200 —
—
7.8
t_CK
2)3)4)5)
µs
2)3)4)5)12)
1) 0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5 V ± 0.2 V, V_DD = +2.5 V ± 0.2 V (DDR333); V_DDQ = 2.6 V ± 0.1 V, V_DD = +2.6 V ± 0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until V_REF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on t_DQSS.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between V_IH(ac) and V_IL(ac).
11) For each of the terms, if not already an integer, round to the next highest integer. t_CK is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 20 AC Timing - Absolute Specifications DDR266A, DDR266 and DDR200
Parameter
Symbol
–7
DDR266A
–7F
DDR266
-8
DDR200
Unit Note/
Test Condition ¹⁾
DQ output access time
t_AC
from CK/CK
DQS output access time t_DQSCK
from CK/CK
CK high-level width
t_CH
CK low-level width
t_CL
Clock Half Period
t_HP
Clock cycle time
t_CK2.5
t_CK2
DQ and DM input hold time t_DH
DQ and DM input setup t_DS
time
Min. Max. Min. Max. Min.
–0.75 +0.75 –0.75 +0.75 –0.8
Max.
+0.8 ns
–0.75 +0.75 –0.75 +0.75 –0.8 +0.8 ns
0.45 0.55 0.45 0.55 0.45 0.55 t_CK
0.45 0.55 0.45 0.55 0.45 0.55 t_CK
min. (t_CL, t_CH) min. (t_CL, t_CH) min. (t_CL, t_CH) ns
7.5 12 7.5 12 10
12
ns
7.5 12 7.5 12 10
12
ns
0.5 — 0.5 — 0.6 —
ns
0.5 — 0.5 — 0.6 —
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
CL = 2.5 ^2)3)4)5)
CL = 2.0 ^2)3)4)5)
2)3)4)5)
2)3)4)5)
Data Sheet
63
Rev. 1.2, 2004-02
02102004-TSR1-4ZWW