HYB25D256400B Datasheet, PDF (12/83 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM

HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Pin Configuration
CKE
CK
CK
CS
WE
CAS
RAS
Mode
Registers
13
13
A0-A12,
BA0, BA1
15
2
2
11 ^{Column-Address}
Counter/Latch
Bank3
Bank1 ^Bank2
CK, CK
DLL
8192
Bank0
Memory
Array
(8192 x 1024 x 8)
Sense Amplifiers
I/O Gating
DM Mask Logic
1024
(x8)
Column
Decoder
10
COL0
1
8
8
8
Data
4
4
4
DQS
1
Generator
COL0 _Input
Register
Write ^{Mask 1}
1
FIFO
&
Drivers
1
2
84
1
4
clk
out
clk
in
Data
4
4
DQS
1
4
CK,
COL0
CK
1
DQ0-DQ3,
DM
DQS
Figure 3 Block Diagram (64Mb × 4)
Notes:
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
not represent an actual circuit implementation.
2. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and
DQS signals.
Data Sheet
12
Rev. 1.2, 2004-02
02102004-TSR1-4ZWW