HYB25D256400B Datasheet, PDF (29/83 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM

CK
CK
Command
Address
DQS
DQ
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Functional Description
CAS Latency = 2
Read
BAa, COL n
Read
BAa, COL x
CL=2
Read
BAa, COL b
Read
BAa, COL g
NOP
NOP
DOa-n DOa-n' DOa-x DOa-x' DOa-b DOa-b’ DOa-g
CK
CK
Command
Address
DQS
DQ
CAS Latency = 2.5
Read
BAa, COL n
Read
Read
BAa, COL x
BAa, COL b
CL=2.5
Read
BAa, COL g
NOP
NOP
DOa-n DOa-n' DOa-x DOa-x' DOa-b DOa-b’
DO a-n, etc. = data out from bank a, column n etc.
n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted).
Reads are to active rows in any banks.
Shown with nominal t_AC, t_DQSCK, and t_DQSQ.
Don’t Care
Figure 13 Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)
Data from any Read burst may be truncated with a Burst Terminate command, as shown on Figure 14
"Terminating a Read Burst: CAS Latencies (Burst Length = 8)" on Page 30. The Burst Terminate latency is
equal to the read (CAS) latency, i.e. the Burst Terminate command should be issued x cycles after the Read
command, where x equals the number of desired data element pairs.
Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If
truncation is necessary, the Burst Terminate command must be used, as shown on Figure 15 "Read to Write:
CAS Latencies (Burst Length = 4 or 8)" on Page 31. The example is shown for t_DQSS (min). The t_DQSS (max)
case, not shown here, has a longer bus idle time. t_DQSS (min) and t_DQSS (max) are defined in the section on Writes.
A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto
Precharge was not activated). The Precharge command should be issued x cycles after the Read command,
where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This
is shown on Figure 16 "Read to Precharge: CAS Latencies (Burst Length = 4 or 8)" on Page 32 for Read
latencies of 2 and 2.5. Following the Precharge command, a subsequent command to the same bank cannot be
Data Sheet
29
Rev. 1.2, 2004-02
02102004-TSR1-4ZWW