HYB25D256400B Datasheet, PDF (61/83 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM

HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Electrical Characteristics
Table 18 AC Operating Conditions¹⁾
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM Signals
Input Low (Logic 0) Voltage, DQ, DQS and DM Signals
Input Differential Voltage, CK and CK Inputs
Input Closing Point Voltage, CK and CK Inputs
Symbol
Values
Unit Note/
Min.
Max.
Test
Condition
V_IH(AC)
V_IL(AC)
V_ID(AC)
V_IX(AC)
V_REF + 0.31 —
V
—
V_REF – 0.31 V
0.7
V_DDQ + 0.6 V
0.5 × V_DDQ 0.5 × V_DDQ V
– 0.2
+ 0.2
2)3)
2)3)
2)3)4)
2)3)5)
1) V_DDQ = 2.5 V ± 0.2 V, V_DD = +2.5 V ± 0.2 V (DDR200 - DDR333); V_DDQ = 2.6 V ± 0.1 V, V_DD = +2.6 V ± 0.1 V (DDR400);
0 °C ≤ T_A ≤ 70 °C
2) Input slew rate = 1 V/ns.
3) Inputs are not recognized as valid until V_REF stabilizes.
4) V_ID is the magnitude of the difference between the input level on CK and the input level on CK.
5) The value of V_IX is expected to equal 0.5 × V_DDQ of the transmitting device and must track variations in the DC level of the
same.
Table 19 AC Timing - Absolute Specifications for DDR333 and DDR400B
Parameter
Symbol
–6
–5
Unit
DDR333
DDR400B
Min. Max. Min. Max.
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock Half Period
Clock cycle time
t_AC
t_DQSCK
t_CH
t_CL
t_HP
t_CK
–0.7 +0.7 –0.5 +0.5 ns
–0.6 +0.6 –0.6 +0.6 ns
0.45 0.55
0.45 0.55
t_CK
0.45 0.55
0.45 0.55
t_CK
min. (t_CL, t_CH)
min. (t_CL, t_CH) ns
—
—
5
8
ns
7.5 12
6
12
ns
7.5 12
7.5 12
ns
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width
(each input)
DQ and DM input pulse width (each
input)
Data-out high-impedance time from
CK/CK
Data-out low-impedance time from
CK/CK
Write command to 1^st DQS latching
transition
t_DH
t_DS
t_IPW
t_DIPW
t_HZ
t_LZ
t_DQSS
0.45 —
0.4 —
ns
0.45 —
0.4 —
ns
2.2 —
2.2 —
ns
1.75 —
1.75 —
ns
–0.7 +0.7 –0.7 +0.7 ns
–0.7 +0.7 –0.7 +0.7 ns
0.75 1.25
0.75 1.25
t_CK
Note/ Test
Condition ¹⁾
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
CL = 3.0
2)3)4)5)
CL = 2.5
2)3)4)5)
CL = 2.0
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)6)
2)3)4)5)6)
2)3)4)5)7)
2)3)4)5)7)
2)3)4)5)
Data Sheet
61
Rev. 1.2, 2004-02
02102004-TSR1-4ZWW