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HYB25D256400B Datasheet, PDF (51/83 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Functional Description
Table 9 Truth Table 4: Current State Bank n - Command to Bank m (different bank)
Current State CS
Any
H
L
Idle
X
Row Activating, L
Active, or
L
Precharging
L
L
Read (Auto
L
Precharge
L
Disabled)
L
Write (Auto
L
Precharge
L
Disabled)
L
L
Read (With Auto L
Precharge)
L
L
L
Write (With Auto L
Precharge)
L
L
L
RAS CAS WE Command
X X X Deselect
H H H No Operation
X X X Any Command
Otherwise Allowed
to Bank m
L H H Active
H L H Read
H L L Write
L H L Precharge
L H H Active
H L H Read
L H L Precharge
L H H Active
H L H Read
H L L Write
L H L Precharge
L H H Active
H L H Read
H L L Write
L H L Precharge
L H H Active
H L H Read
H L L Write
L H L Precharge
Action
NOP. Continue previous
operation.
NOP. Continue previous
operation.
–
Select and activate row
Select column and start
Read burst
Select column and start Write
burst
–
Select and activate row
Select column and start new
Read burst
–
Select and activate row
Select column and start Read
burst
Select column and start new
Write burst
–
Select and activate row
Select column and start new
Read burst
Select column and start Write
burst
–
Select and activate row
Select column and start Read
burst
Select column and start new
Write burst
–
Notes
1) to 6)2)3)4)5)6)
1) to 6)
1) to 6)
1) to 6)
1) to 7)
1) to 7)
1) to 6)
1) to 6)
1) to 7)
1) to 6)
1) to 6)
1) to 8)
1) to 7)
1) to 6)
1) to 6)
1) to 7), 10)9)
1) to 7), 9), 10)
1) to 6)
1) to 6)
1) to 7), 9)
1) to 7), 9)
1) to 6)
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 7: Clock Enable (CKE) and after tXSNR/tXSRD
has been met (if the previous state was self refresh).
2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands
shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is
allowable). Exceptions are covered in the notes below.
Data Sheet
51
Rev. 1.2, 2004-02
02102004-TSR1-4ZWW