HYB25D256400B Datasheet, PDF (38/83 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM

CK
CK
Command
Address
DQS
DQ
DM
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Functional Description
Maximum DQSS
T1
T2
T3
T4
T5
Write
Write
BAa, COL b
BAa, COL x
t_DQSS (max)
Write
BAa, COL n
Write
BAa, COL a
Write
BAa, COL g
DI a-b DI a-b’
DI a-x
DI a-x’ DI a-n
DI a-n’
DI a-a
DI a-a’
CK
CK
Command
Address
DQS
DQ
DM
Minimum DQSS
T1
T2
T3
T4
T5
Write
Write
BAa, COL b
BAa, COL x
t_DQSS (min)
Write
BAa, COL n
Write
BAa, COL a
Write
BAa, COL g
DI a-b DI a-b’
DI a-x
DI a-x’
DI a-n
DI a-n’
DI a-a
DI a-a’
DI a-g
DI a-b, etc. = data in for bank a, column b, etc.
b', etc. = odd or even complement of b, etc. (i.e., column address LSB inverted).
Each Write command may be to any bank.
Figure 21 Random Write Cycles (Burst Length = 2, 4 or 8)
Don’t Care
Data Sheet
38
Rev. 1.2, 2004-02
02102004-TSR1-4ZWW