HYB25D256400B Datasheet, PDF (28/83 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM

CK
CK
Command
Address
DQS
DQ
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Functional Description
CAS Latency = 2
Read
BAa, COL n
NOP
CL=2
NOP
Read
BAa, COL b
NOP
DO a-n
NOP
DOa- b
CK
CK
Command
Address
Read
BAa, COL n
DQS
DQ
NOP
NOP
CL=2.5
Read
BAa, COL b
DO a-n
CAS Latency = 2.5
NOP
NOP
NOP
DOa- b
DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).
3 subsequent elements of data out appear in the programmed order following DO a-n (and following DO a-b).
Shown with nominal t_AC, t_DQSCK, and t_DQSQ.
Figure 12 Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)
Don’t Care
Data Sheet
28
Rev. 1.2, 2004-02
02102004-TSR1-4ZWW