HYB25D256400B Datasheet, PDF (50/83 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM

HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Functional Description
2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are
those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3) Current state definitions: Idle:The bank has been precharged, and t_RP has been met. Row Active: A row in the bank has
been activated, and t_RCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A
Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A
Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
4) The following states must not be interrupted by a command issued to the same bank. Precharging: Starts with registration
of a Precharge command and ends when t_RP is met. Once t_RP is met, the bank is in the idle state. Row Activating: Starts
with registration of an Active command and ends when t_RCD is met. Once t_RCD is met, the bank is in the “row active” state.
Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when
t_RP has been met. Once t_RP is met, the bank is in the idle state. Write w/Auto Precharge Enabled: Starts with registration
of a Write command with Auto Precharge enabled and ends when t_RP has been met. Once t_RP is met, the bank is in the
idle state. Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge
occurring during these states. Allowable commands to the other bank are determined by its current state& according to
Truth Table 4.
5) The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied
on each positive clock edge during these states. Refreshing: Starts with registration of an Auto Refresh command and
ends when t_RFC is met. Once t_RFC is met, the DDR SDRAM is in the “all banks idle” state. Accessing Mode Register: Starts
with registration of a Mode Register Set command and ends when tMRD has been met. Once t_MRD is met, the DDR
SDRAM is in the “all banks idle” state. Precharging All: Starts with registration of a Precharge All command and ends
when t_RP is met. Once t_RP is met, all banks is in the idle state.
6) All states and sequences not shown are illegal or reserved.
7) Not bank-specific; requires that all banks are idle.
8) May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
9) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.
10) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads
or Writes with Auto Precharge disabled.
11) Requires appropriate DM masking.
Data Sheet
50
Rev. 1.2, 2004-02
02102004-TSR1-4ZWW