HYB25D256400B Datasheet, PDF (18/83 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM

HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Functional Description
Notes:
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the
block.
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within
the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps
within the block.
3.2.3 Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and
the availability of the first burst of output data. The latency can be programmed 2, 2.5 or 3 clocks. CAS latency of
1.5 is an optional feature on this device. If a Read command is registered at clock edge n, and the latency is m
clocks, the data is available nominally coincident with clock edge n + m (see Figure 6). Reserved states should
not be used as unknown operation or incompatibility with future versions may result.
Data Sheet
18
Rev. 1.2, 2004-02
02102004-TSR1-4ZWW