HYB25D256400B Datasheet, PDF (14/83 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM

HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Pin Configuration
CKE
CK
CK
CS
WE
CAS
RAS
Mode
Registers
13
13
A0-A11,
BA0, BA1
15
2
2
9
Column-Address
Counter/Latch
Bank3
Bank1 ^Bank2
CK, CK
DLL
8192
Bank0
Memory
Array
(8192 x 256x 32)
Sense Amplifiers
I/O Gating
DM Mask Logic
256
(x32)
Column
Decoder
8
COL0
1
32
32
32
Data
16
16
16
DQS
1
Generator
COL0 _Input
DQS
Register
Write ^{Mask 1}
FIFO
&
Drivers
1
2
32 ¹⁶
1
1
1
16
16
clk
out
clk
in
Data
16
16
CK,
COL0
CK
2
DQ0-DQ15,
DM
LDQS, UDQS
Figure 5 Block^NDiag^Tr^haⁱ m^F (16ⁱMb^l ×^Bl 16^k)^Di
i i d d f ili
d
di f h
if
Notes:
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
not represent an actual circuit implementation.
2. UDM and LDM are unidirectional signals (input only), but is internally loaded to match the load of the
bidirectional DQ, UDQS and LDQS signals.
Data Sheet
14
Rev. 1.2, 2004-02
02102004-TSR1-4ZWW