HYB25D256400B Datasheet, PDF (30/83 Pages) Infineon Technologies AG – 256 Mbit Double Data Rate SDRAM

HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Functional Description
issued until t_RP is met. Note that part of the row precharge time is hidden during the access of the last data
elements.
In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as
described above) provides the same operation that would result from the same Read burst with Auto Precharge
enabled. The disadvantage of the Precharge command is that it requires that the command and address busses
be available at the appropriate time to issue the command. The advantage of the Precharge command is that it
can be used to truncate bursts.
CK
CK
Command
Address
DQS
DQ
CK
CK
Command
Address
DQS
DQ
CAS Latency = 2
Read
BAa, COL n
NOP
CL=2
BST
NOP
NOP
NOP
DOa-n
No further output data after this point.
DQS tristated.
CAS Latency = 2.5
Read
BAa, COL n
NOP
BST
NOP
NOP
NOP
CL=2.5
DOa-n
No further output data after this point.
DQS tristated.
DO a-n = data out from bank a, column n.
Cases shown are bursts of 8 terminated after 4 data elements.
3 subsequent elements of data out appear in the programmed order following DO a-n.
Shown with nominal t_AC, t_DQSCK, and t_DQSQ.
Figure 14 Terminating a Read Burst: CAS Latencies (Burst Length = 8)
Don’t Care
Data Sheet
30
Rev. 1.2, 2004-02
02102004-TSR1-4ZWW